[sigrok-firmware-fx2lafw.git] / sainsmart_dds120.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE() PA7 = 1

#define SET_COUPLING(x) set_coupling(x)

#define SET_CALIBRATION_PULSE(x) set_calibration_pulse(x)

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04

#define LED_CLEAR() NOP
#define LED_GREEN() NOP
#define LED_RED()   NOP

#define TIMER2_VAL 1000

/* CTLx pin index (IFCLK, ADC clock input). */
#define CTL_BIT 2

#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter && (--ledcounter == 0))
		LED_CLEAR();

	TF2 = 0;
}

/**
 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage
 * (attentuator). The second stage is then doing the gain by 3 different
 * resistor values switched into the feedback loop.
 *
 * #Channel 0:
 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 =  -8dB
 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 =  -6dB
 * PC1=0; PC2=0; PC3= 1 -> Gain x1   =   0dB
 * PC1=0; PC2=1; PC3= 0 -> Gain x2   =  +6dB
 *
 * #Channel 1:
 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB 
 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 =  -8dB
 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 =  -6dB
 * PE1=0; PC4=0; PC5= 1 -> Gain x1   =   0dB
 * PE1=0; PC4=1; PC5= 0 -> Gain x2   =  +6dB
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits_C, bit_E, mask_C, mask_E;

	if (channel == 0) {
		mask_C = 0x0E;
		mask_E = 0x00;
		bit_E = 0;
		switch (val) {
		case 1:
			bits_C = 0x02;
			break;
		case 2:
			bits_C = 0x06;
			break;
		case 5:
			bits_C = 0x00;
			break;
		case 10:
			bits_C = 0x04;
			break;
		case 20:
			bits_C = 0x08;
			break;
		default:
			return FALSE;
		}
	} else if (channel == 1) {
		mask_C = 0x30;
		mask_E = 0x02;
		switch (val) {
		case 1:
			bits_C = 0x00;
			bit_E = 0x02; 
			break;
		case 2:
			bits_C = 0x10;
			bit_E = 0x02; 
			break;
		case 5:
			bits_C = 0x00;
			bit_E = 0x00; 
			break;
		case 10:
			bits_C = 0x10;
			bit_E = 0x00; 
			break;
		case 20:
			bits_C = 0x20;
			bit_E = 0x00; 
			break;
		default:
			return FALSE;
		}
	} else {
		return FALSE;
	}
	IOC = (IOC & ~mask_C) | (bits_C & mask_C);
	IOE = (IOE & ~mask_E) | (bit_E & mask_E);
		
	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	LED_GREEN();
	ledcounter = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, OUT0, 0xea },
	{ 16,    1,   1, 2, 0, OUT0, 0xea },
	{ 15,    1,   0, 2, 1, OUT0, 0xaa },
	{ 12,    2,   1, 2, 0, OUT0, 0xea },
	{ 11,    1,   1, 2, 0, OUT0, 0xaa },
	{  8,    3,   2, 2, 0, OUT0, 0xea },
	{  6,    2,   2, 2, 0, OUT0, 0xaa },
	{  5,    3,   2, 2, 0, OUT0, 0xaa },
	{  4,    6,   5, 2, 0, OUT0, 0xea },
	{  3,    5,   4, 2, 0, OUT0, 0xaa },
	{  2,   12,  11, 2, 0, OUT0, 0xea },
	{  1,   24,  23, 2, 0, OUT0, 0xea },
	{ 50,   48,  47, 2, 0, OUT0, 0xea },
	{ 20,  120, 119, 2, 0, OUT0, 0xea },
	{ 10,  240, 239, 2, 0, OUT0, 0xea },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED, clear after timeout. */
	LED_RED();
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		SET_COUPLING(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		SET_CALIBRATION_PULSE(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -TIMER2_VAL & 0xff;
	RCAP2H = (-TIMER2_VAL & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTECFG = 0;
	PORTCCFG = 0;
	PORTACFG = 0;
	OEE = 0xff;
	OEC = 0xff;
	OEA = 0xff;

	SET_ANALOG_MODE();

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
ce1d0a86 BL	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
ce1d0a86 BL	19	*/
	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE() PA7 = 1
be6d306d UH	28
297fb13a UH	29	#define SET_COUPLING(x) set_coupling(x)
	30
	31	#define SET_CALIBRATION_PULSE(x) set_calibration_pulse(x)
	32
e583c3fc UH	33	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	34	/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
	35	#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04
	36
65b34f7e UH	37	#define LED_CLEAR() NOP
	38	#define LED_GREEN() NOP
	39	#define LED_RED() NOP
	40
2c57c00b UH	41	#define TIMER2_VAL 1000
2c57c00b UH	42
e1c5ba21 UH	43	/* CTLx pin index (IFCLK, ADC clock input). */
	44	#define CTL_BIT 2
	45
	46	#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
	47	#define OE_CTL (((1 << CTL_BIT) << 4) \| (1 << CTL_BIT)) /* OEx = CTLx = 1 */
	48
ce1d0a86 BL	49	/* Change to support as many interfaces as you need. */
	50	static BYTE altiface = 0;
	51
65b34f7e UH	52	static volatile WORD ledcounter = 0;
65b34f7e UH	53
ce1d0a86 BL	54	static volatile __bit dosud = FALSE;
	55	static volatile __bit dosuspend = FALSE;
	56
	57	extern __code BYTE highspd_dscr;
	58	extern __code BYTE fullspd_dscr;
	59
	60	void resume_isr(void) __interrupt RESUME_ISR
	61	{
	62	CLEAR_RESUME();
	63	}
	64
	65	void sudav_isr(void) __interrupt SUDAV_ISR
	66	{
	67	dosud = TRUE;
	68	CLEAR_SUDAV();
	69	}
	70
	71	void usbreset_isr(void) __interrupt USBRESET_ISR
	72	{
	73	handle_hispeed(FALSE);
	74	CLEAR_USBRESET();
	75	}
	76
	77	void hispeed_isr(void) __interrupt HISPEED_ISR
	78	{
	79	handle_hispeed(TRUE);
	80	CLEAR_HISPEED();
	81	}
	82
	83	void suspend_isr(void) __interrupt SUSPEND_ISR
	84	{
	85	dosuspend = TRUE;
	86	CLEAR_SUSPEND();
	87	}
	88
	89	void timer2_isr(void) __interrupt TF2_ISR
	90	{
e583c3fc UH	91	TOGGLE_CALIBRATION_PIN();
e583c3fc UH	92
65b34f7e UH	93	if (ledcounter && (--ledcounter == 0))
	94	LED_CLEAR();
	95
ce1d0a86 BL	96	TF2 = 0;
	97	}
	98
	99	/**
3968bbfb UH	100	* The gain stage is 2 stage approach. -6dB and -20dB on the first stage
	101	* (attentuator). The second stage is then doing the gain by 3 different
	102	* resistor values switched into the feedback loop.
	103	*
ce1d0a86 BL	104	* #Channel 0:
	105	* PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
	106	* PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
	107	* PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
	108	* PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
	109	* PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
	110	* PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
3968bbfb	111	*
ce1d0a86 BL	112	* #Channel 1:
	113	* PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
	114	* PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
	115	* PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
	116	* PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
	117	* PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
	118	* PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
	119	*/
	120	static BOOL set_voltage(BYTE channel, BYTE val)
	121	{
	122	BYTE bits_C, bit_E, mask_C, mask_E;
	123
	124	if (channel == 0) {
	125	mask_C = 0x0E;
	126	mask_E = 0x00;
	127	bit_E = 0;
	128	switch (val) {
	129	case 1:
	130	bits_C = 0x02;
	131	break;
	132	case 2:
	133	bits_C = 0x06;
	134	break;
	135	case 5:
	136	bits_C = 0x00;
	137	break;
	138	case 10:
	139	bits_C = 0x04;
	140	break;
	141	case 20:
	142	bits_C = 0x08;
	143	break;
	144	default:
	145	return FALSE;
	146	}
	147	} else if (channel == 1) {
	148	mask_C = 0x30;
	149	mask_E = 0x02;
	150	switch (val) {
	151	case 1:
	152	bits_C = 0x00;
	153	bit_E = 0x02;
	154	break;
	155	case 2:
	156	bits_C = 0x10;
	157	bit_E = 0x02;
	158	break;
	159	case 5:
	160	bits_C = 0x00;
	161	bit_E = 0x00;
	162	break;
	163	case 10:
	164	bits_C = 0x10;
	165	bit_E = 0x00;
	166	break;
	167	case 20:
	168	bits_C = 0x20;
	169	bit_E = 0x00;
	170	break;
	171	default:
	172	return FALSE;
	173	}
	174	} else {
	175	return FALSE;
176	}
177	IOC = (IOC & ~mask_C) \| (bits_C & mask_C);
178	IOE = (IOE & ~mask_E) \| (bit_E & mask_E);
179
180	return TRUE;
181	}
182
75ad0fa5 BL	183	/**
	184	* Each LSB in the nibble of the byte controls the coupling per channel.
	185	*
	186	* Setting PE3 disables AC coupling capacitor on CH0.
	187	* Setting PE0 disables AC coupling capacitor on CH1.
	188	*/
	189	static void set_coupling(BYTE coupling_cfg)
	190	{
	191	if (coupling_cfg & 0x01)
	192	IOE \|= 0x08;
	193	else
	194	IOE &= ~0x08;
	195
	196	if (coupling_cfg & 0x10)
	197	IOE \|= 0x01;
	198	else
	199	IOE &= ~0x01;
	200	}
	201
ce1d0a86 BL	202	static BOOL set_numchannels(BYTE numchannels)
	203	{
	204	if (numchannels == 1 \|\| numchannels == 2) {
	205	BYTE fifocfg = 7 + numchannels;
	206	EP2FIFOCFG = fifocfg;
	207	EP6FIFOCFG = fifocfg;
	208	return TRUE;
	209	}
	210
	211	return FALSE;
	212	}
	213
	214	static void clear_fifo(void)
	215	{
	216	GPIFABORT = 0xff;
	217	SYNCDELAY3;
	218	FIFORESET = 0x80;
	219	SYNCDELAY3;
	220	FIFORESET = 0x82;
	221	SYNCDELAY3;
	222	FIFORESET = 0x86;
	223	SYNCDELAY3;
	224	FIFORESET = 0;
	225	}
	226
	227	static void stop_sampling(void)
	228	{
	229	GPIFABORT = 0xff;
	230	SYNCDELAY3;
	231	INPKTEND = (altiface == 0) ? 6 : 2;
	232	}
	233
	234	static void start_sampling(void)
	235	{
	236	int i;
	237
be6d306d UH	238	SET_ANALOG_MODE();
be6d306d UH	239
ce1d0a86 BL	240	clear_fifo();
	241
	242	for (i = 0; i < 1000; i++);
	243
	244	while (!(GPIFTRIG & 0x80))
	245	;
	246
	247	SYNCDELAY3;
	248	GPIFTCB1 = 0x28;
	249	SYNCDELAY3;
	250	GPIFTCB0 = 0;
	251	GPIFTRIG = (altiface == 0) ? 6 : 4;
	252
65b34f7e UH	253	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	254	LED_GREEN();
	255	ledcounter = 0;
ce1d0a86 BL	256	}
	257
	258	static void select_interface(BYTE alt)
	259	{
	260	const BYTE *pPacketSize = \
	261	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	262	+ (9 + (16 * alt) + 9 + 4);
	263
	264	altiface = alt;
	265
	266	if (alt == 0) {
	267	/* Bulk on EP6. */
	268	EP2CFG = 0x00;
	269	EP6CFG = 0xe0;
	270	EP6GPIFFLGSEL = 1;
	271	EP6AUTOINLENL = pPacketSize[0];
	272	EP6AUTOINLENH = pPacketSize[1];
	273	} else {
	274	/* Iso on EP2. */
	275	EP2CFG = 0xd8;
	276	EP6CFG = 0x00;
	277	EP2GPIFFLGSEL = 1;
	278	EP2AUTOINLENL = pPacketSize[0];
	279	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	280	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	281	}
	282	}
	283
	284	static const struct samplerate_info {
	285	BYTE rate;
	286	BYTE wait0;
	287	BYTE wait1;
	288	BYTE opc0;
	289	BYTE opc1;
	290	BYTE out0;
	291	BYTE ifcfg;
	292	} samplerates[] = {
	293	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	294	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
e1c5ba21 UH	295	{ 24, 1, 0, 2, 1, OUT0, 0xea },
	296	{ 16, 1, 1, 2, 0, OUT0, 0xea },
	297	{ 15, 1, 0, 2, 1, OUT0, 0xaa },
	298	{ 12, 2, 1, 2, 0, OUT0, 0xea },
	299	{ 11, 1, 1, 2, 0, OUT0, 0xaa },
	300	{ 8, 3, 2, 2, 0, OUT0, 0xea },
	301	{ 6, 2, 2, 2, 0, OUT0, 0xaa },
	302	{ 5, 3, 2, 2, 0, OUT0, 0xaa },
	303	{ 4, 6, 5, 2, 0, OUT0, 0xea },
	304	{ 3, 5, 4, 2, 0, OUT0, 0xaa },
	305	{ 2, 12, 11, 2, 0, OUT0, 0xea },
	306	{ 1, 24, 23, 2, 0, OUT0, 0xea },
	307	{ 50, 48, 47, 2, 0, OUT0, 0xea },
	308	{ 20, 120, 119, 2, 0, OUT0, 0xea },
	309	{ 10, 240, 239, 2, 0, OUT0, 0xea },
ce1d0a86 BL	310	};
	311
	312	static BOOL set_samplerate(BYTE rate)
	313	{
	314	BYTE i = 0;
	315
	316	while (samplerates[i].rate != rate) {
	317	i++;
	318	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	319	return FALSE;
	320	}
	321
	322	IFCONFIG = samplerates[i].ifcfg;
	323
	324	AUTOPTRSETUP = 7;
24373950	325	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
ce1d0a86 BL	326	AUTOPTRL2 = 0x00;
	327
	328	/*
	329	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	330	* wait 24, CTLx=0, FIFO
	331	* wait 23, CTLx=1
	332	* jump 0, CTLx=1
ce1d0a86 BL	333	*
ce1d0a86 BL	334	* The program for 24 MHz is:
3968bbfb UH	335	* wait 1, CTLx=0, FIFO
3968bbfb UH	336	* jump 0, CTLx=1
ce1d0a86 BL	337	*
ce1d0a86 BL	338	* The program for 30/48 MHz is:
3968bbfb UH	339	* jump 0, CTLx=Z, FIFO, LOOP
	340	*
	341	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
ce1d0a86 BL	342	*/
ce1d0a86 BL	343
24373950	344	/* LENGTH / BRANCH 0-7 */
ce1d0a86 BL	345	EXTAUTODAT2 = samplerates[i].wait0;
	346	EXTAUTODAT2 = samplerates[i].wait1;
	347	EXTAUTODAT2 = 1;
	348	EXTAUTODAT2 = 0;
	349	EXTAUTODAT2 = 0;
	350	EXTAUTODAT2 = 0;
	351	EXTAUTODAT2 = 0;
	352	EXTAUTODAT2 = 0;
	353
24373950	354	/* OPCODE 0-7 */
ce1d0a86 BL	355	EXTAUTODAT2 = samplerates[i].opc0;
ce1d0a86 BL	356	EXTAUTODAT2 = samplerates[i].opc1;
24373950	357	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
ce1d0a86 BL	358	EXTAUTODAT2 = 0;
	359	EXTAUTODAT2 = 0;
	360	EXTAUTODAT2 = 0;
	361	EXTAUTODAT2 = 0;
	362	EXTAUTODAT2 = 0;
	363
24373950	364	/* OUTPUT 0-7 */
ce1d0a86	365	EXTAUTODAT2 = samplerates[i].out0;
e1c5ba21 UH	366	EXTAUTODAT2 = OE_CTL;
e1c5ba21 UH	367	EXTAUTODAT2 = OE_CTL;
24373950 UH	368	EXTAUTODAT2 = 0;
	369	EXTAUTODAT2 = 0;
	370	EXTAUTODAT2 = 0;
	371	EXTAUTODAT2 = 0;
	372	EXTAUTODAT2 = 0;
ce1d0a86	373
24373950	374	/* LOGIC FUNCTION 0-7 */
ce1d0a86 BL	375	EXTAUTODAT2 = 0;
	376	EXTAUTODAT2 = 0;
	377	EXTAUTODAT2 = 0;
	378	EXTAUTODAT2 = 0;
	379	EXTAUTODAT2 = 0;
	380	EXTAUTODAT2 = 0;
	381	EXTAUTODAT2 = 0;
	382	EXTAUTODAT2 = 0;
	383
	384	for (i = 0; i < 96; i++)
	385	EXTAUTODAT2 = 0;
	386
	387	return TRUE;
	388	}
	389
a425fae9 BL	390	static BOOL set_calibration_pulse(BYTE fs)
	391	{
	392	switch (fs) {
	393	case 0: // 100Hz
	394	RCAP2L = -10000 & 0xff;
386296a7	395	RCAP2H = (-10000 & 0xff00) >> 8;
a425fae9 BL	396	return TRUE;
	397	case 1: // 1kHz
	398	RCAP2L = -1000 & 0xff;
386296a7	399	RCAP2H = (-1000 & 0xff00) >> 8;
a425fae9 BL	400	return TRUE;
a425fae9 BL	401	case 10: // 1kHz
386296a7	402	RCAP2L = (BYTE)(-100 & 0xff);
a425fae9 BL	403	RCAP2H = 0xff;
	404	return TRUE;
	405	case 50: // 50kHz
386296a7	406	RCAP2L = (BYTE)(-20 & 0xff);
a425fae9 BL	407	RCAP2H = 0xff;
	408	return TRUE;
	409	default:
	410	return FALSE;
	411	}
	412	}
	413
ce1d0a86 BL	414	/* Set alt_ifc to the current alt interface for ifc. /
	415	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	416	{
	417	(void)ifc;
	418
	419	*alt_ifc = altiface;
	420
	421	return TRUE;
	422	}
	423
	424	/*
	425	* Return TRUE if you set the interface requested.
	426	*
	427	* Note: This function should reconfigure and reset the endpoints
	428	* according to the interface descriptors you provided.
	429	*/
	430	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	431	{
	432	if (ifc == 0)
	433	select_interface(alt_ifc);
	434
	435	return TRUE;
	436	}
	437
	438	BYTE handle_get_configuration(void)
	439	{
	440	/* We only support configuration 0. */
	441	return 0;
	442	}
	443
	444	BOOL handle_set_configuration(BYTE cfg)
	445	{
	446	/* We only support configuration 0. */
	447	(void)cfg;
	448
	449	return TRUE;
	450	}
	451
	452	BOOL handle_vendorcommand(BYTE cmd)
	453	{
	454	stop_sampling();
	455
65b34f7e UH	456	/* Set red LED, clear after timeout. */
	457	LED_RED();
	458	ledcounter = 1000;
	459
ce1d0a86	460	/* Clear EP0BCH/L for each valid command. */
a425fae9	461	if (cmd >= 0xe0 && cmd <= 0xe6) {
ce1d0a86 BL	462	EP0BCH = 0;
	463	EP0BCL = 0;
	464	while (EP0CS & bmEPBUSY);
	465	}
	466
	467	switch (cmd) {
	468	case 0xe0:
	469	case 0xe1:
	470	set_voltage(cmd - 0xe0, EP0BUF[0]);
	471	return TRUE;
	472	case 0xe2:
	473	set_samplerate(EP0BUF[0]);
	474	return TRUE;
	475	case 0xe3:
	476	if (EP0BUF[0] == 1)
	477	start_sampling();
	478	return TRUE;
	479	case 0xe4:
	480	set_numchannels(EP0BUF[0]);
	481	return TRUE;
75ad0fa5	482	case 0xe5:
297fb13a	483	SET_COUPLING(EP0BUF[0]);
75ad0fa5	484	return TRUE;
a425fae9	485	case 0xe6:
297fb13a	486	SET_CALIBRATION_PULSE(EP0BUF[0]);
a425fae9	487	return TRUE;
ce1d0a86 BL	488	}
	489
	490	return FALSE; /* Not handled by handlers. */
	491	}
	492
	493	static void init(void)
	494	{
	495	EP4CFG = 0;
	496	EP8CFG = 0;
	497
be6d306d UH	498	SET_ANALOG_MODE();
be6d306d UH	499
ce1d0a86	500	/* In idle mode tristate all outputs. */
24373950 UH	501	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	502	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
ce1d0a86 BL	503	GPIFWFSELECT = 0x00;
	504	GPIFREADYSTAT = 0x00;
	505
	506	stop_sampling();
	507
	508	set_voltage(0, 1);
	509	set_voltage(1, 1);
	510	set_samplerate(1);
	511	set_numchannels(2);
	512	select_interface(0);
	513	}
	514
	515	static void main(void)
	516	{
	517	/* Save energy. */
	518	SETCPUFREQ(CLK_12M);
	519
	520	init();
	521
	522	/* Set up interrupts. */
	523	USE_USB_INTS();
	524
	525	ENABLE_SUDAV();
	526	ENABLE_USBRESET();
	527	ENABLE_HISPEED();
	528	ENABLE_SUSPEND();
	529	ENABLE_RESUME();
	530
	531	/* Global (8051) interrupt enable. */
	532	EA = 1;
	533
	534	/* Init timer2. */
2c57c00b UH	535	RCAP2L = -TIMER2_VAL & 0xff;
2c57c00b UH	536	RCAP2H = (-TIMER2_VAL & 0xff00) >> 8;
ce1d0a86 BL	537	T2CON = 0;
	538	ET2 = 1;
	539	TR2 = 1;
	540
	541	RENUMERATE_UNCOND();
	542
4d971e01	543	PORTECFG = 0;
ce1d0a86 BL	544	PORTCCFG = 0;
ce1d0a86 BL	545	PORTACFG = 0;
4d971e01	546	OEE = 0xff;
ce1d0a86	547	OEC = 0xff;
4d971e01	548	OEA = 0xff;
ce1d0a86	549
be6d306d	550	SET_ANALOG_MODE();
ce1d0a86 BL	551
	552	while (TRUE) {
	553	if (dosud) {
	554	dosud = FALSE;
	555	handle_setupdata();
	556	}
	557
	558	if (dosuspend) {
	559	dosuspend = FALSE;
	560	do {
	561	/* Make sure ext wakeups are cleared. */
3968bbfb	562	WAKEUPCS \|= bmWU \| bmWU2;
ce1d0a86 BL	563	SUSPEND = 1;
	564	PCON \|= 1;
	565	__asm
	566	nop
	567	nop
	568	nop
	569	nop
	570	nop
	571	nop
	572	nop
	573	__endasm;
	574	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	575
	576	/* Resume (TRM 6.4). */
	577	if (REMOTE_WAKEUP()) {
	578	delay(5);
	579	USBCS \|= bmSIGRESUME;
	580	delay(15);
	581	USBCS &= ~bmSIGRESUME;
	582	}
	583	}
	584	}
	585	}