[sigrok-firmware-fx2lafw.git] / sainsmart_dds120.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE() PA7 = 1

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	TF2 = 0;
}

/**
 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage
 * (attentuator). The second stage is then doing the gain by 3 different
 * resistor values switched into the feedback loop.
 *
 * #Channel 0:
 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 =  -8dB
 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 =  -6dB
 * PC1=0; PC2=0; PC3= 1 -> Gain x1   =   0dB
 * PC1=0; PC2=1; PC3= 0 -> Gain x2   =  +6dB
 *
 * #Channel 1:
 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB 
 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 =  -8dB
 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 =  -6dB
 * PE1=0; PC4=0; PC5= 1 -> Gain x1   =   0dB
 * PE1=0; PC4=1; PC5= 0 -> Gain x2   =  +6dB
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits_C, bit_E, mask_C, mask_E;

	if (channel == 0) {
		mask_C = 0x0E;
		mask_E = 0x00;
		bit_E = 0;
		switch (val) {
		case 1:
			bits_C = 0x02;
			break;
		case 2:
			bits_C = 0x06;
			break;
		case 5:
			bits_C = 0x00;
			break;
		case 10:
			bits_C = 0x04;
			break;
		case 20:
			bits_C = 0x08;
			break;
		default:
			return FALSE;
		}
	} else if (channel == 1) {
		mask_C = 0x30;
		mask_E = 0x02;
		switch (val) {
		case 1:
			bits_C = 0x00;
			bit_E = 0x02; 
			break;
		case 2:
			bits_C = 0x10;
			bit_E = 0x02; 
			break;
		case 5:
			bits_C = 0x00;
			bit_E = 0x00; 
			break;
		case 10:
			bits_C = 0x10;
			bit_E = 0x00; 
			break;
		case 20:
			bits_C = 0x20;
			bit_E = 0x00; 
			break;
		default:
			return FALSE;
		}
	} else {
		return FALSE;
	}
	IOC = (IOC & ~mask_C) | (bits_C & mask_C);
	IOE = (IOE & ~mask_E) | (bit_E & mask_E);
		
	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, 0x40, 0xea },
	{ 16,    1,   1, 2, 0, 0x40, 0xea },
	{ 15,    1,   0, 2, 1, 0x40, 0xaa },
	{ 12,    2,   1, 2, 0, 0x40, 0xea },
	{ 11,    1,   1, 2, 0, 0x40, 0xaa },
	{  8,    3,   2, 2, 0, 0x40, 0xea },
	{  6,    2,   2, 2, 0, 0x40, 0xaa },
	{  5,    3,   2, 2, 0, 0x40, 0xaa },
	{  4,    6,   5, 2, 0, 0x40, 0xea },
	{  3,    5,   4, 2, 0, 0x40, 0xaa },
	{  2,   12,  11, 2, 0, 0x40, 0xea },
	{  1,   24,  23, 2, 0, 0x40, 0xea },
	{ 50,   48,  47, 2, 0, 0x40, 0xea },
	{ 20,  120, 119, 2, 0, 0x40, 0xea },
	{ 10,  240, 239, 2, 0, 0x40, 0xea },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		set_coupling(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		set_calibration_pulse(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -1000 & 0xff;
	RCAP2H = (-1000 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTCCFG = 0;
	PORTACFG = 0;
	PORTECFG = 0;
	OEE = 0xFF;
	OEC = 0xff;
	OEA = 0x80;

	SET_ANALOG_MODE();

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
ce1d0a86 BL	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
ce1d0a86 BL	19	*/
	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE() PA7 = 1
be6d306d UH	28
e583c3fc UH	29	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	30	/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
	31	#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04
	32
ce1d0a86 BL	33	/* Change to support as many interfaces as you need. */
	34	static BYTE altiface = 0;
	35
	36	static volatile __bit dosud = FALSE;
	37	static volatile __bit dosuspend = FALSE;
	38
	39	extern __code BYTE highspd_dscr;
	40	extern __code BYTE fullspd_dscr;
	41
	42	void resume_isr(void) __interrupt RESUME_ISR
	43	{
	44	CLEAR_RESUME();
	45	}
	46
	47	void sudav_isr(void) __interrupt SUDAV_ISR
	48	{
	49	dosud = TRUE;
	50	CLEAR_SUDAV();
	51	}
	52
	53	void usbreset_isr(void) __interrupt USBRESET_ISR
	54	{
	55	handle_hispeed(FALSE);
	56	CLEAR_USBRESET();
	57	}
	58
	59	void hispeed_isr(void) __interrupt HISPEED_ISR
	60	{
	61	handle_hispeed(TRUE);
	62	CLEAR_HISPEED();
	63	}
	64
	65	void suspend_isr(void) __interrupt SUSPEND_ISR
	66	{
	67	dosuspend = TRUE;
	68	CLEAR_SUSPEND();
	69	}
	70
	71	void timer2_isr(void) __interrupt TF2_ISR
	72	{
e583c3fc UH	73	TOGGLE_CALIBRATION_PIN();
e583c3fc UH	74
ce1d0a86 BL	75	TF2 = 0;
	76	}
	77
	78	/**
3968bbfb UH	79	* The gain stage is 2 stage approach. -6dB and -20dB on the first stage
	80	* (attentuator). The second stage is then doing the gain by 3 different
	81	* resistor values switched into the feedback loop.
	82	*
ce1d0a86 BL	83	* #Channel 0:
	84	* PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
	85	* PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
	86	* PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
	87	* PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
	88	* PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
	89	* PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
3968bbfb	90	*
ce1d0a86 BL	91	* #Channel 1:
	92	* PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
	93	* PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
	94	* PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
	95	* PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
	96	* PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
	97	* PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
	98	*/
	99	static BOOL set_voltage(BYTE channel, BYTE val)
	100	{
	101	BYTE bits_C, bit_E, mask_C, mask_E;
	102
	103	if (channel == 0) {
	104	mask_C = 0x0E;
	105	mask_E = 0x00;
	106	bit_E = 0;
	107	switch (val) {
	108	case 1:
	109	bits_C = 0x02;
	110	break;
	111	case 2:
	112	bits_C = 0x06;
	113	break;
	114	case 5:
	115	bits_C = 0x00;
	116	break;
	117	case 10:
	118	bits_C = 0x04;
	119	break;
	120	case 20:
	121	bits_C = 0x08;
	122	break;
	123	default:
	124	return FALSE;
	125	}
	126	} else if (channel == 1) {
	127	mask_C = 0x30;
	128	mask_E = 0x02;
	129	switch (val) {
	130	case 1:
	131	bits_C = 0x00;
	132	bit_E = 0x02;
	133	break;
	134	case 2:
	135	bits_C = 0x10;
	136	bit_E = 0x02;
	137	break;
	138	case 5:
	139	bits_C = 0x00;
	140	bit_E = 0x00;
	141	break;
	142	case 10:
	143	bits_C = 0x10;
	144	bit_E = 0x00;
	145	break;
	146	case 20:
	147	bits_C = 0x20;
	148	bit_E = 0x00;
	149	break;
	150	default:
	151	return FALSE;
	152	}
	153	} else {
	154	return FALSE;
155	}
156	IOC = (IOC & ~mask_C) \| (bits_C & mask_C);
157	IOE = (IOE & ~mask_E) \| (bit_E & mask_E);
158
159	return TRUE;
160	}
161
75ad0fa5 BL	162	/**
	163	* Each LSB in the nibble of the byte controls the coupling per channel.
	164	*
	165	* Setting PE3 disables AC coupling capacitor on CH0.
	166	* Setting PE0 disables AC coupling capacitor on CH1.
	167	*/
	168	static void set_coupling(BYTE coupling_cfg)
	169	{
	170	if (coupling_cfg & 0x01)
	171	IOE \|= 0x08;
	172	else
	173	IOE &= ~0x08;
	174
	175	if (coupling_cfg & 0x10)
	176	IOE \|= 0x01;
	177	else
	178	IOE &= ~0x01;
	179	}
	180
ce1d0a86 BL	181	static BOOL set_numchannels(BYTE numchannels)
	182	{
	183	if (numchannels == 1 \|\| numchannels == 2) {
	184	BYTE fifocfg = 7 + numchannels;
	185	EP2FIFOCFG = fifocfg;
	186	EP6FIFOCFG = fifocfg;
	187	return TRUE;
	188	}
	189
	190	return FALSE;
	191	}
	192
	193	static void clear_fifo(void)
	194	{
	195	GPIFABORT = 0xff;
	196	SYNCDELAY3;
	197	FIFORESET = 0x80;
	198	SYNCDELAY3;
	199	FIFORESET = 0x82;
	200	SYNCDELAY3;
	201	FIFORESET = 0x86;
	202	SYNCDELAY3;
	203	FIFORESET = 0;
	204	}
	205
	206	static void stop_sampling(void)
	207	{
	208	GPIFABORT = 0xff;
	209	SYNCDELAY3;
	210	INPKTEND = (altiface == 0) ? 6 : 2;
	211	}
	212
	213	static void start_sampling(void)
	214	{
	215	int i;
	216
be6d306d UH	217	SET_ANALOG_MODE();
be6d306d UH	218
ce1d0a86 BL	219	clear_fifo();
	220
	221	for (i = 0; i < 1000; i++);
	222
	223	while (!(GPIFTRIG & 0x80))
	224	;
	225
	226	SYNCDELAY3;
	227	GPIFTCB1 = 0x28;
	228	SYNCDELAY3;
	229	GPIFTCB0 = 0;
	230	GPIFTRIG = (altiface == 0) ? 6 : 4;
	231
	232	}
	233
	234	static void select_interface(BYTE alt)
	235	{
	236	const BYTE *pPacketSize = \
	237	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	238	+ (9 + (16 * alt) + 9 + 4);
	239
	240	altiface = alt;
	241
	242	if (alt == 0) {
	243	/* Bulk on EP6. */
	244	EP2CFG = 0x00;
	245	EP6CFG = 0xe0;
	246	EP6GPIFFLGSEL = 1;
	247	EP6AUTOINLENL = pPacketSize[0];
	248	EP6AUTOINLENH = pPacketSize[1];
	249	} else {
	250	/* Iso on EP2. */
	251	EP2CFG = 0xd8;
	252	EP6CFG = 0x00;
	253	EP2GPIFFLGSEL = 1;
	254	EP2AUTOINLENL = pPacketSize[0];
	255	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	256	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	257	}
	258	}
	259
	260	static const struct samplerate_info {
	261	BYTE rate;
	262	BYTE wait0;
	263	BYTE wait1;
	264	BYTE opc0;
	265	BYTE opc1;
	266	BYTE out0;
	267	BYTE ifcfg;
	268	} samplerates[] = {
	269	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	270	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
	271	{ 24, 1, 0, 2, 1, 0x40, 0xea },
	272	{ 16, 1, 1, 2, 0, 0x40, 0xea },
33c275bb	273	{ 15, 1, 0, 2, 1, 0x40, 0xaa },
ce1d0a86	274	{ 12, 2, 1, 2, 0, 0x40, 0xea },
33c275bb	275	{ 11, 1, 1, 2, 0, 0x40, 0xaa },
ce1d0a86	276	{ 8, 3, 2, 2, 0, 0x40, 0xea },
33c275bb BL	277	{ 6, 2, 2, 2, 0, 0x40, 0xaa },
33c275bb BL	278	{ 5, 3, 2, 2, 0, 0x40, 0xaa },
ce1d0a86	279	{ 4, 6, 5, 2, 0, 0x40, 0xea },
33c275bb	280	{ 3, 5, 4, 2, 0, 0x40, 0xaa },
ce1d0a86 BL	281	{ 2, 12, 11, 2, 0, 0x40, 0xea },
	282	{ 1, 24, 23, 2, 0, 0x40, 0xea },
	283	{ 50, 48, 47, 2, 0, 0x40, 0xea },
	284	{ 20, 120, 119, 2, 0, 0x40, 0xea },
	285	{ 10, 240, 239, 2, 0, 0x40, 0xea },
	286	};
	287
	288	static BOOL set_samplerate(BYTE rate)
	289	{
	290	BYTE i = 0;
	291
	292	while (samplerates[i].rate != rate) {
	293	i++;
	294	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	295	return FALSE;
	296	}
	297
	298	IFCONFIG = samplerates[i].ifcfg;
	299
	300	AUTOPTRSETUP = 7;
24373950	301	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
ce1d0a86 BL	302	AUTOPTRL2 = 0x00;
	303
	304	/*
	305	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	306	* wait 24, CTLx=0, FIFO
	307	* wait 23, CTLx=1
	308	* jump 0, CTLx=1
ce1d0a86 BL	309	*
ce1d0a86 BL	310	* The program for 24 MHz is:
3968bbfb UH	311	* wait 1, CTLx=0, FIFO
3968bbfb UH	312	* jump 0, CTLx=1
ce1d0a86 BL	313	*
ce1d0a86 BL	314	* The program for 30/48 MHz is:
3968bbfb UH	315	* jump 0, CTLx=Z, FIFO, LOOP
	316	*
	317	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
ce1d0a86 BL	318	*/
ce1d0a86 BL	319
24373950	320	/* LENGTH / BRANCH 0-7 */
ce1d0a86 BL	321	EXTAUTODAT2 = samplerates[i].wait0;
	322	EXTAUTODAT2 = samplerates[i].wait1;
	323	EXTAUTODAT2 = 1;
	324	EXTAUTODAT2 = 0;
	325	EXTAUTODAT2 = 0;
	326	EXTAUTODAT2 = 0;
	327	EXTAUTODAT2 = 0;
	328	EXTAUTODAT2 = 0;
	329
24373950	330	/* OPCODE 0-7 */
ce1d0a86 BL	331	EXTAUTODAT2 = samplerates[i].opc0;
ce1d0a86 BL	332	EXTAUTODAT2 = samplerates[i].opc1;
24373950	333	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
ce1d0a86 BL	334	EXTAUTODAT2 = 0;
	335	EXTAUTODAT2 = 0;
	336	EXTAUTODAT2 = 0;
	337	EXTAUTODAT2 = 0;
	338	EXTAUTODAT2 = 0;
	339
24373950	340	/* OUTPUT 0-7 */
ce1d0a86	341	EXTAUTODAT2 = samplerates[i].out0;
3968bbfb UH	342	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
3968bbfb UH	343	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
24373950 UH	344	EXTAUTODAT2 = 0;
	345	EXTAUTODAT2 = 0;
	346	EXTAUTODAT2 = 0;
	347	EXTAUTODAT2 = 0;
	348	EXTAUTODAT2 = 0;
ce1d0a86	349
24373950	350	/* LOGIC FUNCTION 0-7 */
ce1d0a86 BL	351	EXTAUTODAT2 = 0;
	352	EXTAUTODAT2 = 0;
	353	EXTAUTODAT2 = 0;
	354	EXTAUTODAT2 = 0;
	355	EXTAUTODAT2 = 0;
	356	EXTAUTODAT2 = 0;
	357	EXTAUTODAT2 = 0;
	358	EXTAUTODAT2 = 0;
	359
	360	for (i = 0; i < 96; i++)
	361	EXTAUTODAT2 = 0;
	362
	363	return TRUE;
	364	}
	365
a425fae9 BL	366	static BOOL set_calibration_pulse(BYTE fs)
	367	{
	368	switch (fs) {
	369	case 0: // 100Hz
	370	RCAP2L = -10000 & 0xff;
386296a7	371	RCAP2H = (-10000 & 0xff00) >> 8;
a425fae9 BL	372	return TRUE;
	373	case 1: // 1kHz
	374	RCAP2L = -1000 & 0xff;
386296a7	375	RCAP2H = (-1000 & 0xff00) >> 8;
a425fae9 BL	376	return TRUE;
a425fae9 BL	377	case 10: // 1kHz
386296a7	378	RCAP2L = (BYTE)(-100 & 0xff);
a425fae9 BL	379	RCAP2H = 0xff;
	380	return TRUE;
	381	case 50: // 50kHz
386296a7	382	RCAP2L = (BYTE)(-20 & 0xff);
a425fae9 BL	383	RCAP2H = 0xff;
	384	return TRUE;
	385	default:
	386	return FALSE;
	387	}
	388	}
	389
ce1d0a86 BL	390	/* Set alt_ifc to the current alt interface for ifc. /
	391	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	392	{
	393	(void)ifc;
	394
	395	*alt_ifc = altiface;
	396
	397	return TRUE;
	398	}
	399
	400	/*
	401	* Return TRUE if you set the interface requested.
	402	*
	403	* Note: This function should reconfigure and reset the endpoints
	404	* according to the interface descriptors you provided.
	405	*/
	406	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	407	{
	408	if (ifc == 0)
	409	select_interface(alt_ifc);
	410
	411	return TRUE;
	412	}
	413
	414	BYTE handle_get_configuration(void)
	415	{
	416	/* We only support configuration 0. */
	417	return 0;
	418	}
	419
	420	BOOL handle_set_configuration(BYTE cfg)
	421	{
	422	/* We only support configuration 0. */
	423	(void)cfg;
	424
	425	return TRUE;
	426	}
	427
	428	BOOL handle_vendorcommand(BYTE cmd)
	429	{
	430	stop_sampling();
	431
	432	/* Clear EP0BCH/L for each valid command. */
a425fae9	433	if (cmd >= 0xe0 && cmd <= 0xe6) {
ce1d0a86 BL	434	EP0BCH = 0;
	435	EP0BCL = 0;
	436	while (EP0CS & bmEPBUSY);
	437	}
	438
	439	switch (cmd) {
	440	case 0xe0:
	441	case 0xe1:
	442	set_voltage(cmd - 0xe0, EP0BUF[0]);
	443	return TRUE;
	444	case 0xe2:
	445	set_samplerate(EP0BUF[0]);
	446	return TRUE;
	447	case 0xe3:
	448	if (EP0BUF[0] == 1)
	449	start_sampling();
	450	return TRUE;
	451	case 0xe4:
	452	set_numchannels(EP0BUF[0]);
	453	return TRUE;
75ad0fa5 BL	454	case 0xe5:
	455	set_coupling(EP0BUF[0]);
	456	return TRUE;
a425fae9 BL	457	case 0xe6:
	458	set_calibration_pulse(EP0BUF[0]);
	459	return TRUE;
ce1d0a86 BL	460	}
	461
	462	return FALSE; /* Not handled by handlers. */
	463	}
	464
	465	static void init(void)
	466	{
	467	EP4CFG = 0;
	468	EP8CFG = 0;
	469
be6d306d UH	470	SET_ANALOG_MODE();
be6d306d UH	471
ce1d0a86	472	/* In idle mode tristate all outputs. */
24373950 UH	473	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	474	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
ce1d0a86 BL	475	GPIFWFSELECT = 0x00;
	476	GPIFREADYSTAT = 0x00;
	477
	478	stop_sampling();
	479
	480	set_voltage(0, 1);
	481	set_voltage(1, 1);
	482	set_samplerate(1);
	483	set_numchannels(2);
	484	select_interface(0);
	485	}
	486
	487	static void main(void)
	488	{
	489	/* Save energy. */
	490	SETCPUFREQ(CLK_12M);
	491
	492	init();
	493
	494	/* Set up interrupts. */
	495	USE_USB_INTS();
	496
	497	ENABLE_SUDAV();
	498	ENABLE_USBRESET();
	499	ENABLE_HISPEED();
	500	ENABLE_SUSPEND();
	501	ENABLE_RESUME();
	502
	503	/* Global (8051) interrupt enable. */
	504	EA = 1;
	505
	506	/* Init timer2. */
	507	RCAP2L = -1000 & 0xff;
386296a7	508	RCAP2H = (-1000 & 0xff00) >> 8;
ce1d0a86 BL	509	T2CON = 0;
	510	ET2 = 1;
	511	TR2 = 1;
	512
	513	RENUMERATE_UNCOND();
	514
	515	PORTCCFG = 0;
	516	PORTACFG = 0;
	517	PORTECFG = 0;
	518	OEE = 0xFF;
	519	OEC = 0xff;
	520	OEA = 0x80;
	521
be6d306d	522	SET_ANALOG_MODE();
ce1d0a86 BL	523
	524	while (TRUE) {
	525	if (dosud) {
	526	dosud = FALSE;
	527	handle_setupdata();
	528	}
	529
	530	if (dosuspend) {
	531	dosuspend = FALSE;
	532	do {
	533	/* Make sure ext wakeups are cleared. */
3968bbfb	534	WAKEUPCS \|= bmWU \| bmWU2;
ce1d0a86 BL	535	SUSPEND = 1;
	536	PCON \|= 1;
	537	__asm
	538	nop
	539	nop
	540	nop
	541	nop
	542	nop
	543	nop
	544	nop
	545	__endasm;
	546	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	547
	548	/* Resume (TRM 6.4). */
	549	if (REMOTE_WAKEUP()) {
	550	delay(5);
	551	USBCS \|= bmSIGRESUME;
	552	delay(15);
	553	USBCS &= ~bmSIGRESUME;
	554	}
	555	}
	556	}
	557	}