[sigrok-firmware-fx2lafw.git] / sainsmart_dds120.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE() PA7 = 1

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04

#define LED_CLEAR() NOP
#define LED_GREEN() NOP
#define LED_RED()   NOP

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter && (--ledcounter == 0))
		LED_CLEAR();

	TF2 = 0;
}

/**
 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage
 * (attentuator). The second stage is then doing the gain by 3 different
 * resistor values switched into the feedback loop.
 *
 * #Channel 0:
 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 =  -8dB
 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 =  -6dB
 * PC1=0; PC2=0; PC3= 1 -> Gain x1   =   0dB
 * PC1=0; PC2=1; PC3= 0 -> Gain x2   =  +6dB
 *
 * #Channel 1:
 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB 
 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 =  -8dB
 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 =  -6dB
 * PE1=0; PC4=0; PC5= 1 -> Gain x1   =   0dB
 * PE1=0; PC4=1; PC5= 0 -> Gain x2   =  +6dB
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits_C, bit_E, mask_C, mask_E;

	if (channel == 0) {
		mask_C = 0x0E;
		mask_E = 0x00;
		bit_E = 0;
		switch (val) {
		case 1:
			bits_C = 0x02;
			break;
		case 2:
			bits_C = 0x06;
			break;
		case 5:
			bits_C = 0x00;
			break;
		case 10:
			bits_C = 0x04;
			break;
		case 20:
			bits_C = 0x08;
			break;
		default:
			return FALSE;
		}
	} else if (channel == 1) {
		mask_C = 0x30;
		mask_E = 0x02;
		switch (val) {
		case 1:
			bits_C = 0x00;
			bit_E = 0x02; 
			break;
		case 2:
			bits_C = 0x10;
			bit_E = 0x02; 
			break;
		case 5:
			bits_C = 0x00;
			bit_E = 0x00; 
			break;
		case 10:
			bits_C = 0x10;
			bit_E = 0x00; 
			break;
		case 20:
			bits_C = 0x20;
			bit_E = 0x00; 
			break;
		default:
			return FALSE;
		}
	} else {
		return FALSE;
	}
	IOC = (IOC & ~mask_C) | (bits_C & mask_C);
	IOE = (IOE & ~mask_E) | (bit_E & mask_E);
		
	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	LED_GREEN();
	ledcounter = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, 0x40, 0xea },
	{ 16,    1,   1, 2, 0, 0x40, 0xea },
	{ 15,    1,   0, 2, 1, 0x40, 0xaa },
	{ 12,    2,   1, 2, 0, 0x40, 0xea },
	{ 11,    1,   1, 2, 0, 0x40, 0xaa },
	{  8,    3,   2, 2, 0, 0x40, 0xea },
	{  6,    2,   2, 2, 0, 0x40, 0xaa },
	{  5,    3,   2, 2, 0, 0x40, 0xaa },
	{  4,    6,   5, 2, 0, 0x40, 0xea },
	{  3,    5,   4, 2, 0, 0x40, 0xaa },
	{  2,   12,  11, 2, 0, 0x40, 0xea },
	{  1,   24,  23, 2, 0, 0x40, 0xea },
	{ 50,   48,  47, 2, 0, 0x40, 0xea },
	{ 20,  120, 119, 2, 0, 0x40, 0xea },
	{ 10,  240, 239, 2, 0, 0x40, 0xea },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED, clear after timeout. */
	LED_RED();
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		set_coupling(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		set_calibration_pulse(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -1000 & 0xff;
	RCAP2H = (-1000 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTECFG = 0;
	PORTCCFG = 0;
	PORTACFG = 0;
	OEE = 0xff;
	OEC = 0xff;
	OEA = 0xff;

	SET_ANALOG_MODE();

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
ce1d0a86 BL	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
ce1d0a86 BL	19	*/
	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE() PA7 = 1
be6d306d UH	28
e583c3fc UH	29	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	30	/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
	31	#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04
	32
65b34f7e UH	33	#define LED_CLEAR() NOP
	34	#define LED_GREEN() NOP
	35	#define LED_RED() NOP
	36
ce1d0a86 BL	37	/* Change to support as many interfaces as you need. */
	38	static BYTE altiface = 0;
	39
65b34f7e UH	40	static volatile WORD ledcounter = 0;
65b34f7e UH	41
ce1d0a86 BL	42	static volatile __bit dosud = FALSE;
	43	static volatile __bit dosuspend = FALSE;
	44
	45	extern __code BYTE highspd_dscr;
	46	extern __code BYTE fullspd_dscr;
	47
	48	void resume_isr(void) __interrupt RESUME_ISR
	49	{
	50	CLEAR_RESUME();
	51	}
	52
	53	void sudav_isr(void) __interrupt SUDAV_ISR
	54	{
	55	dosud = TRUE;
	56	CLEAR_SUDAV();
	57	}
	58
	59	void usbreset_isr(void) __interrupt USBRESET_ISR
	60	{
	61	handle_hispeed(FALSE);
	62	CLEAR_USBRESET();
	63	}
	64
	65	void hispeed_isr(void) __interrupt HISPEED_ISR
	66	{
	67	handle_hispeed(TRUE);
	68	CLEAR_HISPEED();
	69	}
	70
	71	void suspend_isr(void) __interrupt SUSPEND_ISR
	72	{
	73	dosuspend = TRUE;
	74	CLEAR_SUSPEND();
	75	}
	76
	77	void timer2_isr(void) __interrupt TF2_ISR
	78	{
e583c3fc UH	79	TOGGLE_CALIBRATION_PIN();
e583c3fc UH	80
65b34f7e UH	81	if (ledcounter && (--ledcounter == 0))
	82	LED_CLEAR();
	83
ce1d0a86 BL	84	TF2 = 0;
	85	}
	86
	87	/**
3968bbfb UH	88	* The gain stage is 2 stage approach. -6dB and -20dB on the first stage
	89	* (attentuator). The second stage is then doing the gain by 3 different
	90	* resistor values switched into the feedback loop.
	91	*
ce1d0a86 BL	92	* #Channel 0:
	93	* PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
	94	* PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
	95	* PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
	96	* PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
	97	* PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
	98	* PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
3968bbfb	99	*
ce1d0a86 BL	100	* #Channel 1:
	101	* PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
	102	* PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
	103	* PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
	104	* PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
	105	* PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
	106	* PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
	107	*/
	108	static BOOL set_voltage(BYTE channel, BYTE val)
	109	{
	110	BYTE bits_C, bit_E, mask_C, mask_E;
	111
	112	if (channel == 0) {
	113	mask_C = 0x0E;
	114	mask_E = 0x00;
	115	bit_E = 0;
	116	switch (val) {
	117	case 1:
	118	bits_C = 0x02;
	119	break;
	120	case 2:
	121	bits_C = 0x06;
	122	break;
	123	case 5:
	124	bits_C = 0x00;
	125	break;
	126	case 10:
	127	bits_C = 0x04;
	128	break;
	129	case 20:
	130	bits_C = 0x08;
	131	break;
	132	default:
	133	return FALSE;
	134	}
	135	} else if (channel == 1) {
	136	mask_C = 0x30;
	137	mask_E = 0x02;
	138	switch (val) {
	139	case 1:
	140	bits_C = 0x00;
	141	bit_E = 0x02;
	142	break;
	143	case 2:
	144	bits_C = 0x10;
	145	bit_E = 0x02;
	146	break;
	147	case 5:
	148	bits_C = 0x00;
	149	bit_E = 0x00;
	150	break;
	151	case 10:
	152	bits_C = 0x10;
	153	bit_E = 0x00;
	154	break;
	155	case 20:
	156	bits_C = 0x20;
	157	bit_E = 0x00;
	158	break;
	159	default:
	160	return FALSE;
	161	}
	162	} else {
	163	return FALSE;
164	}
165	IOC = (IOC & ~mask_C) \| (bits_C & mask_C);
166	IOE = (IOE & ~mask_E) \| (bit_E & mask_E);
167
168	return TRUE;
169	}
170
75ad0fa5 BL	171	/**
	172	* Each LSB in the nibble of the byte controls the coupling per channel.
	173	*
	174	* Setting PE3 disables AC coupling capacitor on CH0.
	175	* Setting PE0 disables AC coupling capacitor on CH1.
	176	*/
	177	static void set_coupling(BYTE coupling_cfg)
	178	{
	179	if (coupling_cfg & 0x01)
	180	IOE \|= 0x08;
	181	else
	182	IOE &= ~0x08;
	183
	184	if (coupling_cfg & 0x10)
	185	IOE \|= 0x01;
	186	else
	187	IOE &= ~0x01;
	188	}
	189
ce1d0a86 BL	190	static BOOL set_numchannels(BYTE numchannels)
	191	{
	192	if (numchannels == 1 \|\| numchannels == 2) {
	193	BYTE fifocfg = 7 + numchannels;
	194	EP2FIFOCFG = fifocfg;
	195	EP6FIFOCFG = fifocfg;
	196	return TRUE;
	197	}
	198
	199	return FALSE;
	200	}
	201
	202	static void clear_fifo(void)
	203	{
	204	GPIFABORT = 0xff;
	205	SYNCDELAY3;
	206	FIFORESET = 0x80;
	207	SYNCDELAY3;
	208	FIFORESET = 0x82;
	209	SYNCDELAY3;
	210	FIFORESET = 0x86;
	211	SYNCDELAY3;
	212	FIFORESET = 0;
	213	}
	214
	215	static void stop_sampling(void)
	216	{
	217	GPIFABORT = 0xff;
	218	SYNCDELAY3;
	219	INPKTEND = (altiface == 0) ? 6 : 2;
	220	}
	221
	222	static void start_sampling(void)
	223	{
	224	int i;
	225
be6d306d UH	226	SET_ANALOG_MODE();
be6d306d UH	227
ce1d0a86 BL	228	clear_fifo();
	229
	230	for (i = 0; i < 1000; i++);
	231
	232	while (!(GPIFTRIG & 0x80))
	233	;
	234
	235	SYNCDELAY3;
	236	GPIFTCB1 = 0x28;
	237	SYNCDELAY3;
	238	GPIFTCB0 = 0;
	239	GPIFTRIG = (altiface == 0) ? 6 : 4;
	240
65b34f7e UH	241	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	242	LED_GREEN();
	243	ledcounter = 0;
ce1d0a86 BL	244	}
	245
	246	static void select_interface(BYTE alt)
	247	{
	248	const BYTE *pPacketSize = \
	249	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	250	+ (9 + (16 * alt) + 9 + 4);
	251
	252	altiface = alt;
	253
	254	if (alt == 0) {
	255	/* Bulk on EP6. */
	256	EP2CFG = 0x00;
	257	EP6CFG = 0xe0;
	258	EP6GPIFFLGSEL = 1;
	259	EP6AUTOINLENL = pPacketSize[0];
	260	EP6AUTOINLENH = pPacketSize[1];
	261	} else {
	262	/* Iso on EP2. */
	263	EP2CFG = 0xd8;
	264	EP6CFG = 0x00;
	265	EP2GPIFFLGSEL = 1;
	266	EP2AUTOINLENL = pPacketSize[0];
	267	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	268	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	269	}
	270	}
	271
	272	static const struct samplerate_info {
	273	BYTE rate;
	274	BYTE wait0;
	275	BYTE wait1;
	276	BYTE opc0;
	277	BYTE opc1;
	278	BYTE out0;
	279	BYTE ifcfg;
	280	} samplerates[] = {
	281	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	282	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
	283	{ 24, 1, 0, 2, 1, 0x40, 0xea },
	284	{ 16, 1, 1, 2, 0, 0x40, 0xea },
33c275bb	285	{ 15, 1, 0, 2, 1, 0x40, 0xaa },
ce1d0a86	286	{ 12, 2, 1, 2, 0, 0x40, 0xea },
33c275bb	287	{ 11, 1, 1, 2, 0, 0x40, 0xaa },
ce1d0a86	288	{ 8, 3, 2, 2, 0, 0x40, 0xea },
33c275bb BL	289	{ 6, 2, 2, 2, 0, 0x40, 0xaa },
33c275bb BL	290	{ 5, 3, 2, 2, 0, 0x40, 0xaa },
ce1d0a86	291	{ 4, 6, 5, 2, 0, 0x40, 0xea },
33c275bb	292	{ 3, 5, 4, 2, 0, 0x40, 0xaa },
ce1d0a86 BL	293	{ 2, 12, 11, 2, 0, 0x40, 0xea },
	294	{ 1, 24, 23, 2, 0, 0x40, 0xea },
	295	{ 50, 48, 47, 2, 0, 0x40, 0xea },
	296	{ 20, 120, 119, 2, 0, 0x40, 0xea },
	297	{ 10, 240, 239, 2, 0, 0x40, 0xea },
	298	};
	299
	300	static BOOL set_samplerate(BYTE rate)
	301	{
	302	BYTE i = 0;
	303
	304	while (samplerates[i].rate != rate) {
	305	i++;
	306	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	307	return FALSE;
	308	}
	309
	310	IFCONFIG = samplerates[i].ifcfg;
	311
	312	AUTOPTRSETUP = 7;
24373950	313	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
ce1d0a86 BL	314	AUTOPTRL2 = 0x00;
	315
	316	/*
	317	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	318	* wait 24, CTLx=0, FIFO
	319	* wait 23, CTLx=1
	320	* jump 0, CTLx=1
ce1d0a86 BL	321	*
ce1d0a86 BL	322	* The program for 24 MHz is:
3968bbfb UH	323	* wait 1, CTLx=0, FIFO
3968bbfb UH	324	* jump 0, CTLx=1
ce1d0a86 BL	325	*
ce1d0a86 BL	326	* The program for 30/48 MHz is:
3968bbfb UH	327	* jump 0, CTLx=Z, FIFO, LOOP
	328	*
	329	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
ce1d0a86 BL	330	*/
ce1d0a86 BL	331
24373950	332	/* LENGTH / BRANCH 0-7 */
ce1d0a86 BL	333	EXTAUTODAT2 = samplerates[i].wait0;
	334	EXTAUTODAT2 = samplerates[i].wait1;
	335	EXTAUTODAT2 = 1;
	336	EXTAUTODAT2 = 0;
	337	EXTAUTODAT2 = 0;
	338	EXTAUTODAT2 = 0;
	339	EXTAUTODAT2 = 0;
	340	EXTAUTODAT2 = 0;
	341
24373950	342	/* OPCODE 0-7 */
ce1d0a86 BL	343	EXTAUTODAT2 = samplerates[i].opc0;
ce1d0a86 BL	344	EXTAUTODAT2 = samplerates[i].opc1;
24373950	345	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
ce1d0a86 BL	346	EXTAUTODAT2 = 0;
	347	EXTAUTODAT2 = 0;
	348	EXTAUTODAT2 = 0;
	349	EXTAUTODAT2 = 0;
	350	EXTAUTODAT2 = 0;
	351
24373950	352	/* OUTPUT 0-7 */
ce1d0a86	353	EXTAUTODAT2 = samplerates[i].out0;
3968bbfb UH	354	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
3968bbfb UH	355	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
24373950 UH	356	EXTAUTODAT2 = 0;
	357	EXTAUTODAT2 = 0;
	358	EXTAUTODAT2 = 0;
	359	EXTAUTODAT2 = 0;
	360	EXTAUTODAT2 = 0;
ce1d0a86	361
24373950	362	/* LOGIC FUNCTION 0-7 */
ce1d0a86 BL	363	EXTAUTODAT2 = 0;
	364	EXTAUTODAT2 = 0;
	365	EXTAUTODAT2 = 0;
	366	EXTAUTODAT2 = 0;
	367	EXTAUTODAT2 = 0;
	368	EXTAUTODAT2 = 0;
	369	EXTAUTODAT2 = 0;
	370	EXTAUTODAT2 = 0;
	371
	372	for (i = 0; i < 96; i++)
	373	EXTAUTODAT2 = 0;
	374
	375	return TRUE;
	376	}
	377
a425fae9 BL	378	static BOOL set_calibration_pulse(BYTE fs)
	379	{
	380	switch (fs) {
	381	case 0: // 100Hz
	382	RCAP2L = -10000 & 0xff;
386296a7	383	RCAP2H = (-10000 & 0xff00) >> 8;
a425fae9 BL	384	return TRUE;
	385	case 1: // 1kHz
	386	RCAP2L = -1000 & 0xff;
386296a7	387	RCAP2H = (-1000 & 0xff00) >> 8;
a425fae9 BL	388	return TRUE;
a425fae9 BL	389	case 10: // 1kHz
386296a7	390	RCAP2L = (BYTE)(-100 & 0xff);
a425fae9 BL	391	RCAP2H = 0xff;
	392	return TRUE;
	393	case 50: // 50kHz
386296a7	394	RCAP2L = (BYTE)(-20 & 0xff);
a425fae9 BL	395	RCAP2H = 0xff;
	396	return TRUE;
	397	default:
	398	return FALSE;
	399	}
	400	}
	401
ce1d0a86 BL	402	/* Set alt_ifc to the current alt interface for ifc. /
	403	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	404	{
	405	(void)ifc;
	406
	407	*alt_ifc = altiface;
	408
	409	return TRUE;
	410	}
	411
	412	/*
	413	* Return TRUE if you set the interface requested.
	414	*
	415	* Note: This function should reconfigure and reset the endpoints
	416	* according to the interface descriptors you provided.
	417	*/
	418	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	419	{
	420	if (ifc == 0)
	421	select_interface(alt_ifc);
	422
	423	return TRUE;
	424	}
	425
	426	BYTE handle_get_configuration(void)
	427	{
	428	/* We only support configuration 0. */
	429	return 0;
	430	}
	431
	432	BOOL handle_set_configuration(BYTE cfg)
	433	{
	434	/* We only support configuration 0. */
	435	(void)cfg;
	436
	437	return TRUE;
	438	}
	439
	440	BOOL handle_vendorcommand(BYTE cmd)
	441	{
	442	stop_sampling();
	443
65b34f7e UH	444	/* Set red LED, clear after timeout. */
	445	LED_RED();
	446	ledcounter = 1000;
	447
ce1d0a86	448	/* Clear EP0BCH/L for each valid command. */
a425fae9	449	if (cmd >= 0xe0 && cmd <= 0xe6) {
ce1d0a86 BL	450	EP0BCH = 0;
	451	EP0BCL = 0;
	452	while (EP0CS & bmEPBUSY);
	453	}
	454
	455	switch (cmd) {
	456	case 0xe0:
	457	case 0xe1:
	458	set_voltage(cmd - 0xe0, EP0BUF[0]);
	459	return TRUE;
	460	case 0xe2:
	461	set_samplerate(EP0BUF[0]);
	462	return TRUE;
	463	case 0xe3:
	464	if (EP0BUF[0] == 1)
	465	start_sampling();
	466	return TRUE;
	467	case 0xe4:
	468	set_numchannels(EP0BUF[0]);
	469	return TRUE;
75ad0fa5 BL	470	case 0xe5:
	471	set_coupling(EP0BUF[0]);
	472	return TRUE;
a425fae9 BL	473	case 0xe6:
	474	set_calibration_pulse(EP0BUF[0]);
	475	return TRUE;
ce1d0a86 BL	476	}
	477
	478	return FALSE; /* Not handled by handlers. */
	479	}
	480
	481	static void init(void)
	482	{
	483	EP4CFG = 0;
	484	EP8CFG = 0;
	485
be6d306d UH	486	SET_ANALOG_MODE();
be6d306d UH	487
ce1d0a86	488	/* In idle mode tristate all outputs. */
24373950 UH	489	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	490	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
ce1d0a86 BL	491	GPIFWFSELECT = 0x00;
	492	GPIFREADYSTAT = 0x00;
	493
	494	stop_sampling();
	495
	496	set_voltage(0, 1);
	497	set_voltage(1, 1);
	498	set_samplerate(1);
	499	set_numchannels(2);
	500	select_interface(0);
	501	}
	502
	503	static void main(void)
	504	{
	505	/* Save energy. */
	506	SETCPUFREQ(CLK_12M);
	507
	508	init();
	509
	510	/* Set up interrupts. */
	511	USE_USB_INTS();
	512
	513	ENABLE_SUDAV();
	514	ENABLE_USBRESET();
	515	ENABLE_HISPEED();
	516	ENABLE_SUSPEND();
	517	ENABLE_RESUME();
	518
	519	/* Global (8051) interrupt enable. */
	520	EA = 1;
	521
	522	/* Init timer2. */
	523	RCAP2L = -1000 & 0xff;
386296a7	524	RCAP2H = (-1000 & 0xff00) >> 8;
ce1d0a86 BL	525	T2CON = 0;
	526	ET2 = 1;
	527	TR2 = 1;
	528
	529	RENUMERATE_UNCOND();
	530
4d971e01	531	PORTECFG = 0;
ce1d0a86 BL	532	PORTCCFG = 0;
ce1d0a86 BL	533	PORTACFG = 0;
4d971e01	534	OEE = 0xff;
ce1d0a86	535	OEC = 0xff;
4d971e01	536	OEA = 0xff;
ce1d0a86	537
be6d306d	538	SET_ANALOG_MODE();
ce1d0a86 BL	539
	540	while (TRUE) {
	541	if (dosud) {
	542	dosud = FALSE;
	543	handle_setupdata();
	544	}
	545
	546	if (dosuspend) {
	547	dosuspend = FALSE;
	548	do {
	549	/* Make sure ext wakeups are cleared. */
3968bbfb	550	WAKEUPCS \|= bmWU \| bmWU2;
ce1d0a86 BL	551	SUSPEND = 1;
	552	PCON \|= 1;
	553	__asm
	554	nop
	555	nop
	556	nop
	557	nop
	558	nop
	559	nop
	560	nop
	561	__endasm;
	562	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	563
	564	/* Resume (TRM 6.4). */
	565	if (REMOTE_WAKEUP()) {
	566	delay(5);
	567	USBCS \|= bmSIGRESUME;
	568	delay(15);
	569	USBCS &= ~bmSIGRESUME;
	570	}
	571	}
	572	}
	573	}