[sigrok-firmware-fx2lafw.git] / sainsmart_dds120.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE() PA7 = 1

#define SET_COUPLING(x) set_coupling(x)

#define SET_CALIBRATION_PULSE(x) set_calibration_pulse(x)

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04

#define LED_CLEAR() NOP
#define LED_GREEN() NOP
#define LED_RED()   NOP

/* CTLx pin index (IFCLK, ADC clock input). */
#define CTL_BIT 2

#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter && (--ledcounter == 0))
		LED_CLEAR();

	TF2 = 0;
}

/**
 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage
 * (attentuator). The second stage is then doing the gain by 3 different
 * resistor values switched into the feedback loop.
 *
 * #Channel 0:
 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 =  -8dB
 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 =  -6dB
 * PC1=0; PC2=0; PC3= 1 -> Gain x1   =   0dB
 * PC1=0; PC2=1; PC3= 0 -> Gain x2   =  +6dB
 *
 * #Channel 1:
 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB 
 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 =  -8dB
 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 =  -6dB
 * PE1=0; PC4=0; PC5= 1 -> Gain x1   =   0dB
 * PE1=0; PC4=1; PC5= 0 -> Gain x2   =  +6dB
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits_C, bit_E, mask_C, mask_E;

	if (channel == 0) {
		mask_C = 0x0E;
		mask_E = 0x00;
		bit_E = 0;
		switch (val) {
		case 1:
			bits_C = 0x02;
			break;
		case 2:
			bits_C = 0x06;
			break;
		case 5:
			bits_C = 0x00;
			break;
		case 10:
			bits_C = 0x04;
			break;
		case 20:
			bits_C = 0x08;
			break;
		default:
			return FALSE;
		}
	} else if (channel == 1) {
		mask_C = 0x30;
		mask_E = 0x02;
		switch (val) {
		case 1:
			bits_C = 0x00;
			bit_E = 0x02; 
			break;
		case 2:
			bits_C = 0x10;
			bit_E = 0x02; 
			break;
		case 5:
			bits_C = 0x00;
			bit_E = 0x00; 
			break;
		case 10:
			bits_C = 0x10;
			bit_E = 0x00; 
			break;
		case 20:
			bits_C = 0x20;
			bit_E = 0x00; 
			break;
		default:
			return FALSE;
		}
	} else {
		return FALSE;
	}
	IOC = (IOC & ~mask_C) | (bits_C & mask_C);
	IOE = (IOE & ~mask_E) | (bit_E & mask_E);
		
	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	LED_GREEN();
	ledcounter = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, OUT0, 0xea },
	{ 16,    1,   1, 2, 0, OUT0, 0xea },
	{ 15,    1,   0, 2, 1, OUT0, 0xaa },
	{ 12,    2,   1, 2, 0, OUT0, 0xea },
	{ 11,    1,   1, 2, 0, OUT0, 0xaa },
	{  8,    3,   2, 2, 0, OUT0, 0xea },
	{  6,    2,   2, 2, 0, OUT0, 0xaa },
	{  5,    3,   2, 2, 0, OUT0, 0xaa },
	{  4,    6,   5, 2, 0, OUT0, 0xea },
	{  3,    5,   4, 2, 0, OUT0, 0xaa },
	{  2,   12,  11, 2, 0, OUT0, 0xea },
	{  1,   24,  23, 2, 0, OUT0, 0xea },
	{ 50,   48,  47, 2, 0, OUT0, 0xea },
	{ 20,  120, 119, 2, 0, OUT0, 0xea },
	{ 10,  240, 239, 2, 0, OUT0, 0xea },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED, clear after timeout. */
	LED_RED();
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		SET_COUPLING(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		SET_CALIBRATION_PULSE(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -1000 & 0xff;
	RCAP2H = (-1000 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTECFG = 0;
	PORTCCFG = 0;
	PORTACFG = 0;
	OEE = 0xff;
	OEC = 0xff;
	OEA = 0xff;

	SET_ANALOG_MODE();

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
ce1d0a86 BL	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
ce1d0a86 BL	19	*/
	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE() PA7 = 1
be6d306d UH	28
297fb13a UH	29	#define SET_COUPLING(x) set_coupling(x)
	30
	31	#define SET_CALIBRATION_PULSE(x) set_calibration_pulse(x)
	32
e583c3fc UH	33	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	34	/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
	35	#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04
	36
65b34f7e UH	37	#define LED_CLEAR() NOP
	38	#define LED_GREEN() NOP
	39	#define LED_RED() NOP
	40
e1c5ba21 UH	41	/* CTLx pin index (IFCLK, ADC clock input). */
	42	#define CTL_BIT 2
	43
	44	#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
	45	#define OE_CTL (((1 << CTL_BIT) << 4) \| (1 << CTL_BIT)) /* OEx = CTLx = 1 */
	46
ce1d0a86 BL	47	/* Change to support as many interfaces as you need. */
	48	static BYTE altiface = 0;
	49
65b34f7e UH	50	static volatile WORD ledcounter = 0;
65b34f7e UH	51
ce1d0a86 BL	52	static volatile __bit dosud = FALSE;
	53	static volatile __bit dosuspend = FALSE;
	54
	55	extern __code BYTE highspd_dscr;
	56	extern __code BYTE fullspd_dscr;
	57
	58	void resume_isr(void) __interrupt RESUME_ISR
	59	{
	60	CLEAR_RESUME();
	61	}
	62
	63	void sudav_isr(void) __interrupt SUDAV_ISR
	64	{
	65	dosud = TRUE;
	66	CLEAR_SUDAV();
	67	}
	68
	69	void usbreset_isr(void) __interrupt USBRESET_ISR
	70	{
	71	handle_hispeed(FALSE);
	72	CLEAR_USBRESET();
	73	}
	74
	75	void hispeed_isr(void) __interrupt HISPEED_ISR
	76	{
	77	handle_hispeed(TRUE);
	78	CLEAR_HISPEED();
	79	}
	80
	81	void suspend_isr(void) __interrupt SUSPEND_ISR
	82	{
	83	dosuspend = TRUE;
	84	CLEAR_SUSPEND();
	85	}
	86
	87	void timer2_isr(void) __interrupt TF2_ISR
	88	{
e583c3fc UH	89	TOGGLE_CALIBRATION_PIN();
e583c3fc UH	90
65b34f7e UH	91	if (ledcounter && (--ledcounter == 0))
	92	LED_CLEAR();
	93
ce1d0a86 BL	94	TF2 = 0;
	95	}
	96
	97	/**
3968bbfb UH	98	* The gain stage is 2 stage approach. -6dB and -20dB on the first stage
	99	* (attentuator). The second stage is then doing the gain by 3 different
	100	* resistor values switched into the feedback loop.
	101	*
ce1d0a86 BL	102	* #Channel 0:
	103	* PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
	104	* PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
	105	* PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
	106	* PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
	107	* PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
	108	* PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
3968bbfb	109	*
ce1d0a86 BL	110	* #Channel 1:
	111	* PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
	112	* PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
	113	* PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
	114	* PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
	115	* PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
	116	* PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
	117	*/
	118	static BOOL set_voltage(BYTE channel, BYTE val)
	119	{
	120	BYTE bits_C, bit_E, mask_C, mask_E;
	121
	122	if (channel == 0) {
	123	mask_C = 0x0E;
	124	mask_E = 0x00;
	125	bit_E = 0;
	126	switch (val) {
	127	case 1:
	128	bits_C = 0x02;
	129	break;
	130	case 2:
	131	bits_C = 0x06;
	132	break;
	133	case 5:
	134	bits_C = 0x00;
	135	break;
	136	case 10:
	137	bits_C = 0x04;
	138	break;
	139	case 20:
	140	bits_C = 0x08;
	141	break;
	142	default:
	143	return FALSE;
	144	}
	145	} else if (channel == 1) {
	146	mask_C = 0x30;
	147	mask_E = 0x02;
	148	switch (val) {
	149	case 1:
	150	bits_C = 0x00;
	151	bit_E = 0x02;
	152	break;
	153	case 2:
	154	bits_C = 0x10;
	155	bit_E = 0x02;
	156	break;
	157	case 5:
	158	bits_C = 0x00;
	159	bit_E = 0x00;
	160	break;
	161	case 10:
	162	bits_C = 0x10;
	163	bit_E = 0x00;
	164	break;
	165	case 20:
	166	bits_C = 0x20;
	167	bit_E = 0x00;
	168	break;
	169	default:
	170	return FALSE;
	171	}
	172	} else {
	173	return FALSE;
174	}
175	IOC = (IOC & ~mask_C) \| (bits_C & mask_C);
176	IOE = (IOE & ~mask_E) \| (bit_E & mask_E);
177
178	return TRUE;
179	}
180
75ad0fa5 BL	181	/**
	182	* Each LSB in the nibble of the byte controls the coupling per channel.
	183	*
	184	* Setting PE3 disables AC coupling capacitor on CH0.
	185	* Setting PE0 disables AC coupling capacitor on CH1.
	186	*/
	187	static void set_coupling(BYTE coupling_cfg)
	188	{
	189	if (coupling_cfg & 0x01)
	190	IOE \|= 0x08;
	191	else
	192	IOE &= ~0x08;
	193
	194	if (coupling_cfg & 0x10)
	195	IOE \|= 0x01;
	196	else
	197	IOE &= ~0x01;
	198	}
	199
ce1d0a86 BL	200	static BOOL set_numchannels(BYTE numchannels)
	201	{
	202	if (numchannels == 1 \|\| numchannels == 2) {
	203	BYTE fifocfg = 7 + numchannels;
	204	EP2FIFOCFG = fifocfg;
	205	EP6FIFOCFG = fifocfg;
	206	return TRUE;
	207	}
	208
	209	return FALSE;
	210	}
	211
	212	static void clear_fifo(void)
	213	{
	214	GPIFABORT = 0xff;
	215	SYNCDELAY3;
	216	FIFORESET = 0x80;
	217	SYNCDELAY3;
	218	FIFORESET = 0x82;
	219	SYNCDELAY3;
	220	FIFORESET = 0x86;
	221	SYNCDELAY3;
	222	FIFORESET = 0;
	223	}
	224
	225	static void stop_sampling(void)
	226	{
	227	GPIFABORT = 0xff;
	228	SYNCDELAY3;
	229	INPKTEND = (altiface == 0) ? 6 : 2;
	230	}
	231
	232	static void start_sampling(void)
	233	{
	234	int i;
	235
be6d306d UH	236	SET_ANALOG_MODE();
be6d306d UH	237
ce1d0a86 BL	238	clear_fifo();
	239
	240	for (i = 0; i < 1000; i++);
	241
	242	while (!(GPIFTRIG & 0x80))
	243	;
	244
	245	SYNCDELAY3;
	246	GPIFTCB1 = 0x28;
	247	SYNCDELAY3;
	248	GPIFTCB0 = 0;
	249	GPIFTRIG = (altiface == 0) ? 6 : 4;
	250
65b34f7e UH	251	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	252	LED_GREEN();
	253	ledcounter = 0;
ce1d0a86 BL	254	}
	255
	256	static void select_interface(BYTE alt)
	257	{
	258	const BYTE *pPacketSize = \
	259	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	260	+ (9 + (16 * alt) + 9 + 4);
	261
	262	altiface = alt;
	263
	264	if (alt == 0) {
	265	/* Bulk on EP6. */
	266	EP2CFG = 0x00;
	267	EP6CFG = 0xe0;
	268	EP6GPIFFLGSEL = 1;
	269	EP6AUTOINLENL = pPacketSize[0];
	270	EP6AUTOINLENH = pPacketSize[1];
	271	} else {
	272	/* Iso on EP2. */
	273	EP2CFG = 0xd8;
	274	EP6CFG = 0x00;
	275	EP2GPIFFLGSEL = 1;
	276	EP2AUTOINLENL = pPacketSize[0];
	277	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	278	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	279	}
	280	}
	281
	282	static const struct samplerate_info {
	283	BYTE rate;
	284	BYTE wait0;
	285	BYTE wait1;
	286	BYTE opc0;
	287	BYTE opc1;
	288	BYTE out0;
	289	BYTE ifcfg;
	290	} samplerates[] = {
	291	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	292	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
e1c5ba21 UH	293	{ 24, 1, 0, 2, 1, OUT0, 0xea },
	294	{ 16, 1, 1, 2, 0, OUT0, 0xea },
	295	{ 15, 1, 0, 2, 1, OUT0, 0xaa },
	296	{ 12, 2, 1, 2, 0, OUT0, 0xea },
	297	{ 11, 1, 1, 2, 0, OUT0, 0xaa },
	298	{ 8, 3, 2, 2, 0, OUT0, 0xea },
	299	{ 6, 2, 2, 2, 0, OUT0, 0xaa },
	300	{ 5, 3, 2, 2, 0, OUT0, 0xaa },
	301	{ 4, 6, 5, 2, 0, OUT0, 0xea },
	302	{ 3, 5, 4, 2, 0, OUT0, 0xaa },
	303	{ 2, 12, 11, 2, 0, OUT0, 0xea },
	304	{ 1, 24, 23, 2, 0, OUT0, 0xea },
	305	{ 50, 48, 47, 2, 0, OUT0, 0xea },
	306	{ 20, 120, 119, 2, 0, OUT0, 0xea },
	307	{ 10, 240, 239, 2, 0, OUT0, 0xea },
ce1d0a86 BL	308	};
	309
	310	static BOOL set_samplerate(BYTE rate)
	311	{
	312	BYTE i = 0;
	313
	314	while (samplerates[i].rate != rate) {
	315	i++;
	316	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	317	return FALSE;
	318	}
	319
	320	IFCONFIG = samplerates[i].ifcfg;
	321
	322	AUTOPTRSETUP = 7;
24373950	323	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
ce1d0a86 BL	324	AUTOPTRL2 = 0x00;
	325
	326	/*
	327	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	328	* wait 24, CTLx=0, FIFO
	329	* wait 23, CTLx=1
	330	* jump 0, CTLx=1
ce1d0a86 BL	331	*
ce1d0a86 BL	332	* The program for 24 MHz is:
3968bbfb UH	333	* wait 1, CTLx=0, FIFO
3968bbfb UH	334	* jump 0, CTLx=1
ce1d0a86 BL	335	*
ce1d0a86 BL	336	* The program for 30/48 MHz is:
3968bbfb UH	337	* jump 0, CTLx=Z, FIFO, LOOP
	338	*
	339	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
ce1d0a86 BL	340	*/
ce1d0a86 BL	341
24373950	342	/* LENGTH / BRANCH 0-7 */
ce1d0a86 BL	343	EXTAUTODAT2 = samplerates[i].wait0;
	344	EXTAUTODAT2 = samplerates[i].wait1;
	345	EXTAUTODAT2 = 1;
	346	EXTAUTODAT2 = 0;
	347	EXTAUTODAT2 = 0;
	348	EXTAUTODAT2 = 0;
	349	EXTAUTODAT2 = 0;
	350	EXTAUTODAT2 = 0;
	351
24373950	352	/* OPCODE 0-7 */
ce1d0a86 BL	353	EXTAUTODAT2 = samplerates[i].opc0;
ce1d0a86 BL	354	EXTAUTODAT2 = samplerates[i].opc1;
24373950	355	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
ce1d0a86 BL	356	EXTAUTODAT2 = 0;
	357	EXTAUTODAT2 = 0;
	358	EXTAUTODAT2 = 0;
	359	EXTAUTODAT2 = 0;
	360	EXTAUTODAT2 = 0;
	361
24373950	362	/* OUTPUT 0-7 */
ce1d0a86	363	EXTAUTODAT2 = samplerates[i].out0;
e1c5ba21 UH	364	EXTAUTODAT2 = OE_CTL;
e1c5ba21 UH	365	EXTAUTODAT2 = OE_CTL;
24373950 UH	366	EXTAUTODAT2 = 0;
	367	EXTAUTODAT2 = 0;
	368	EXTAUTODAT2 = 0;
	369	EXTAUTODAT2 = 0;
	370	EXTAUTODAT2 = 0;
ce1d0a86	371
24373950	372	/* LOGIC FUNCTION 0-7 */
ce1d0a86 BL	373	EXTAUTODAT2 = 0;
	374	EXTAUTODAT2 = 0;
	375	EXTAUTODAT2 = 0;
	376	EXTAUTODAT2 = 0;
	377	EXTAUTODAT2 = 0;
	378	EXTAUTODAT2 = 0;
	379	EXTAUTODAT2 = 0;
	380	EXTAUTODAT2 = 0;
	381
	382	for (i = 0; i < 96; i++)
	383	EXTAUTODAT2 = 0;
	384
	385	return TRUE;
	386	}
	387
a425fae9 BL	388	static BOOL set_calibration_pulse(BYTE fs)
	389	{
	390	switch (fs) {
	391	case 0: // 100Hz
	392	RCAP2L = -10000 & 0xff;
386296a7	393	RCAP2H = (-10000 & 0xff00) >> 8;
a425fae9 BL	394	return TRUE;
	395	case 1: // 1kHz
	396	RCAP2L = -1000 & 0xff;
386296a7	397	RCAP2H = (-1000 & 0xff00) >> 8;
a425fae9 BL	398	return TRUE;
a425fae9 BL	399	case 10: // 1kHz
386296a7	400	RCAP2L = (BYTE)(-100 & 0xff);
a425fae9 BL	401	RCAP2H = 0xff;
	402	return TRUE;
	403	case 50: // 50kHz
386296a7	404	RCAP2L = (BYTE)(-20 & 0xff);
a425fae9 BL	405	RCAP2H = 0xff;
	406	return TRUE;
	407	default:
	408	return FALSE;
	409	}
	410	}
	411
ce1d0a86 BL	412	/* Set alt_ifc to the current alt interface for ifc. /
	413	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	414	{
	415	(void)ifc;
	416
	417	*alt_ifc = altiface;
	418
	419	return TRUE;
	420	}
	421
	422	/*
	423	* Return TRUE if you set the interface requested.
	424	*
	425	* Note: This function should reconfigure and reset the endpoints
	426	* according to the interface descriptors you provided.
	427	*/
	428	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	429	{
	430	if (ifc == 0)
	431	select_interface(alt_ifc);
	432
	433	return TRUE;
	434	}
	435
	436	BYTE handle_get_configuration(void)
	437	{
	438	/* We only support configuration 0. */
	439	return 0;
	440	}
	441
	442	BOOL handle_set_configuration(BYTE cfg)
	443	{
	444	/* We only support configuration 0. */
	445	(void)cfg;
	446
	447	return TRUE;
	448	}
	449
	450	BOOL handle_vendorcommand(BYTE cmd)
	451	{
	452	stop_sampling();
	453
65b34f7e UH	454	/* Set red LED, clear after timeout. */
	455	LED_RED();
	456	ledcounter = 1000;
	457
ce1d0a86	458	/* Clear EP0BCH/L for each valid command. */
a425fae9	459	if (cmd >= 0xe0 && cmd <= 0xe6) {
ce1d0a86 BL	460	EP0BCH = 0;
	461	EP0BCL = 0;
	462	while (EP0CS & bmEPBUSY);
	463	}
	464
	465	switch (cmd) {
	466	case 0xe0:
	467	case 0xe1:
	468	set_voltage(cmd - 0xe0, EP0BUF[0]);
	469	return TRUE;
	470	case 0xe2:
	471	set_samplerate(EP0BUF[0]);
	472	return TRUE;
	473	case 0xe3:
	474	if (EP0BUF[0] == 1)
	475	start_sampling();
	476	return TRUE;
	477	case 0xe4:
	478	set_numchannels(EP0BUF[0]);
	479	return TRUE;
75ad0fa5	480	case 0xe5:
297fb13a	481	SET_COUPLING(EP0BUF[0]);
75ad0fa5	482	return TRUE;
a425fae9	483	case 0xe6:
297fb13a	484	SET_CALIBRATION_PULSE(EP0BUF[0]);
a425fae9	485	return TRUE;
ce1d0a86 BL	486	}
	487
	488	return FALSE; /* Not handled by handlers. */
	489	}
	490
	491	static void init(void)
	492	{
	493	EP4CFG = 0;
	494	EP8CFG = 0;
	495
be6d306d UH	496	SET_ANALOG_MODE();
be6d306d UH	497
ce1d0a86	498	/* In idle mode tristate all outputs. */
24373950 UH	499	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	500	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
ce1d0a86 BL	501	GPIFWFSELECT = 0x00;
	502	GPIFREADYSTAT = 0x00;
	503
	504	stop_sampling();
	505
	506	set_voltage(0, 1);
	507	set_voltage(1, 1);
	508	set_samplerate(1);
	509	set_numchannels(2);
	510	select_interface(0);
	511	}
	512
	513	static void main(void)
	514	{
	515	/* Save energy. */
	516	SETCPUFREQ(CLK_12M);
	517
	518	init();
	519
	520	/* Set up interrupts. */
	521	USE_USB_INTS();
	522
	523	ENABLE_SUDAV();
	524	ENABLE_USBRESET();
	525	ENABLE_HISPEED();
	526	ENABLE_SUSPEND();
	527	ENABLE_RESUME();
	528
	529	/* Global (8051) interrupt enable. */
	530	EA = 1;
	531
	532	/* Init timer2. */
	533	RCAP2L = -1000 & 0xff;
386296a7	534	RCAP2H = (-1000 & 0xff00) >> 8;
ce1d0a86 BL	535	T2CON = 0;
	536	ET2 = 1;
	537	TR2 = 1;
	538
	539	RENUMERATE_UNCOND();
	540
4d971e01	541	PORTECFG = 0;
ce1d0a86 BL	542	PORTCCFG = 0;
ce1d0a86 BL	543	PORTACFG = 0;
4d971e01	544	OEE = 0xff;
ce1d0a86	545	OEC = 0xff;
4d971e01	546	OEA = 0xff;
ce1d0a86	547
be6d306d	548	SET_ANALOG_MODE();
ce1d0a86 BL	549
	550	while (TRUE) {
	551	if (dosud) {
	552	dosud = FALSE;
	553	handle_setupdata();
	554	}
	555
	556	if (dosuspend) {
	557	dosuspend = FALSE;
	558	do {
	559	/* Make sure ext wakeups are cleared. */
3968bbfb	560	WAKEUPCS \|= bmWU \| bmWU2;
ce1d0a86 BL	561	SUSPEND = 1;
	562	PCON \|= 1;
	563	__asm
	564	nop
	565	nop
	566	nop
	567	nop
	568	nop
	569	nop
	570	nop
	571	__endasm;
	572	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	573
	574	/* Resume (TRM 6.4). */
	575	if (REMOTE_WAKEUP()) {
	576	delay(5);
	577	USBCS \|= bmSIGRESUME;
	578	delay(15);
	579	USBCS &= ~bmSIGRESUME;
	580	}
	581	}
	582	}
	583	}