[sigrok-firmware-fx2lafw.git] / gpif-acquisition.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#include <eputils.h>
#include <fx2regs.h>
#include <fx2macros.h>
#include <delay.h>
#include <gpif.h>
#include <fx2lafw.h>
#include <gpif-acquisition.h>

__bit gpif_acquiring;

static void gpif_reset_waveforms(void)
{
	int i;

	/* Reset WAVEDATA. */
	AUTOPTRSETUP = 0x03;
	AUTOPTRH1 = 0xe4;
	AUTOPTRL1 = 0x00;
	for (i = 0; i < 128; i++)
		EXTAUTODAT1 = 0;
}

static void gpif_setup_registers(void)
{
	/* TODO. Value probably irrelevant, as we don't use RDY* signals? */
	GPIFREADYCFG = 0;

	/* Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs. */
	GPIFCTLCFG = 0;

	/* When GPIF is idle, tri-state the data bus. */
	/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
	GPIFIDLECS = (0 << 0);

	/* When GPIF is idle, set CTL0-CTL5 to 0. */
	GPIFIDLECTL = 0;

	/*
	 * Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
	 * but not used by us.
	 *
	 * GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
	 *               [3:2] = FIFOWR index, [1:0] = FIFORD index
	 */
	GPIFWFSELECT = (0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0);

	/* Contains RDY* pin values. Read-only according to TRM. */
	GPIFREADYSTAT = 0;

	/* Make GPIF stop on transaction count not flag. */
	EP2GPIFPFSTOP = (0 << 0);
}

static void gpif_init_addr_pins(void)
{
	/*
	 * Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
	 * PORTC[7:0] and PORTE[7]), and output an initial address (zero).
	 * TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
	 */
	PORTCCFG = 0xff;    /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
	OEC = 0xff;         /* Configure PORTC[7:0] as outputs. */
	PORTECFG |= 0x80;   /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
	OEE |= 0x80;        /* Configure PORTE[7] as output. */
	SYNCDELAY();
	GPIFADRL = 0x00;    /* Clear GPIFADR[7:0]. */
	SYNCDELAY();
	GPIFADRH = 0x00;    /* Clear GPIFADR[8]. */
}

static void gpif_init_flowstates(void)
{
	/* Clear all flowstate registers, we don't use this functionality. */
	FLOWSTATE = 0;
	FLOWLOGIC = 0;
	FLOWEQ0CTL = 0;
	FLOWEQ1CTL = 0;
	FLOWHOLDOFF = 0;
	FLOWSTB = 0;
	FLOWSTBEDGE = 0;
	FLOWSTBHPERIOD = 0;
}

void gpif_init_la(void)
{
	/*
	 * Setup the FX2 in GPIF master mode, using the internal clock
	 * (non-inverted) at 48MHz, and using async sampling.
	 */
	IFCONFIG = 0xee;

	/* Abort currently executing GPIF waveform (if any). */
	GPIFABORT = 0xff;

	/* Setup the GPIF registers. */
	gpif_setup_registers();

	/* Reset WAVEDATA. */
	gpif_reset_waveforms();

	/* Initialize GPIF address pins, output initial values. */
	gpif_init_addr_pins();

	/* Initialize flowstate registers (not used by us). */
	gpif_init_flowstates();

	/* Reset the status. */
	gpif_acquiring = FALSE;
}

static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay, uint8_t output)
{
	/*
	 * DELAY
	 * Delay cmd->sample_delay clocks.
	 */
	pSTATE[0] = delay;

	/*
	 * OPCODE
	 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
	 */
	pSTATE[8] = 0;

	/*
	 * OUTPUT
	 * CTL[0:5]=output
	 */
	pSTATE[16] = output;

	/*
	 * LOGIC FUNCTION
	 * Not used.
	 */
	pSTATE[24] = 0x00;
}

static void gpif_make_data_dp_state(volatile BYTE *pSTATE)
{
	/*
	 * BRANCH
	 * Branch to IDLE if condition is true, back to S0 otherwise.
	 */
	pSTATE[0] = (7 << 3) | (0 << 0);

	/*
	 * OPCODE
	 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1
	 */
	pSTATE[8] = (1 << 1) | (1 << 0);

	/*
	 * OUTPUT
	 * CTL[0:5]=0
	 */
	pSTATE[16] = 0x00;

	/*
	 * LOGIC FUNCTION
	 * Evaluate if the FIFO full flag is set.
	 * LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
	 */
	pSTATE[24] = (6 << 3) | (6 << 0);
}

bool gpif_acquisition_start(const struct cmd_start_acquisition *cmd)
{
	int i;
	volatile BYTE *pSTATE = &GPIF_WAVE_DATA;

	/* Ensure GPIF is idle before reconfiguration. */
	while (!(GPIFTRIG & 0x80));

	/* Configure the EP2 FIFO. */
	if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT)
		EP2FIFOCFG = bmAUTOIN | bmWORDWIDE;
	else
		EP2FIFOCFG = bmAUTOIN;
	SYNCDELAY();

	/* Set IFCONFIG to the correct clock source. */
	if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
		IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmASYNC |
			   bmGSTATE | bmIFGPIF;
	} else {
		IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC |
			   bmGSTATE | bmIFGPIF;
	}

	/* Populate delay states. */
	if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) ||
	    cmd->sample_delay_h >= 6)
		return false;

	if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
		uint8_t delay_1, delay_2 = cmd->sample_delay_l;

		/* We need a pulse where the CTL1/2 pins alternate states. */
		if (cmd->sample_delay_h) {
			for (i = 0; i < cmd->sample_delay_h; i++)
				gpif_make_delay_state(pSTATE++, 0, 0x06);
		} else {
			delay_1 = delay_2 / 2;
			delay_2 -= delay_1;
			gpif_make_delay_state(pSTATE++, delay_1, 0x06);
		}

		/* sample_delay_l is always != 0 for the supported rates. */
		gpif_make_delay_state(pSTATE++, delay_2, 0x00);
	} else {
		for (i = 0; i < cmd->sample_delay_h; i++)
			gpif_make_delay_state(pSTATE++, 0, 0x00);

		if (cmd->sample_delay_l != 0)
			gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00);
	}

	/* Populate S1 - the decision point. */
	gpif_make_data_dp_state(pSTATE++);

	/* Execute the whole GPIF waveform once. */
	gpif_set_tc16(1);

	/* Perform the initial GPIF read. */
	gpif_fifo_read(GPIF_EP2);

	/* Update the status. */
	gpif_acquiring = TRUE;

	return true;
}

void gpif_poll(void)
{
	/* Detect if acquisition has completed. */
	if (gpif_acquiring && (GPIFTRIG & 0x80)) {
		/* Activate NAK-ALL to avoid race conditions. */
		FIFORESET = 0x80;
		SYNCDELAY();

		/* Switch to manual mode. */
		EP2FIFOCFG = 0;
		SYNCDELAY();

		/* Reset EP2. */
		FIFORESET = 0x02;
		SYNCDELAY();

		/* Return to auto mode. */
		EP2FIFOCFG = bmAUTOIN;
		SYNCDELAY();

		/* Release NAK-ALL. */
		FIFORESET = 0x00;
		SYNCDELAY();

		gpif_acquiring = FALSE;
	}
}
Commit	Line	Data
e41576ec	1	/*
a986cfff	2	* This file is part of the sigrok-firmware-fx2lafw project.
e41576ec JH	3	*
	4	* Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	*/
	21
293d7e9e	22	#include <eputils.h>
e41576ec JH	23	#include <fx2regs.h>
	24	#include <fx2macros.h>
	25	#include <delay.h>
	26	#include <gpif.h>
e41576ec JH	27	#include <fx2lafw.h>
	28	#include <gpif-acquisition.h>
	29
8819f75c	30	__bit gpif_acquiring;
293d7e9e	31
421e7d6d JH	32	static void gpif_reset_waveforms(void)
	33	{
	34	int i;
e41576ec	35
421e7d6d JH	36	/* Reset WAVEDATA. */
	37	AUTOPTRSETUP = 0x03;
	38	AUTOPTRH1 = 0xe4;
	39	AUTOPTRL1 = 0x00;
	40	for (i = 0; i < 128; i++)
	41	EXTAUTODAT1 = 0;
	42	}
e41576ec JH	43
	44	static void gpif_setup_registers(void)
	45	{
	46	/* TODO. Value probably irrelevant, as we don't use RDY* signals? */
	47	GPIFREADYCFG = 0;
	48
6aa5d1f4	49	/* Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs. */
e41576ec JH	50	GPIFCTLCFG = 0;
	51
	52	/* When GPIF is idle, tri-state the data bus. */
	53	/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
6398a519	54	GPIFIDLECS = (0 << 0);
e41576ec JH	55
	56	/* When GPIF is idle, set CTL0-CTL5 to 0. */
	57	GPIFIDLECTL = 0;
	58
	59	/*
421e7d6d	60	* Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
e41576ec JH	61	* but not used by us.
	62	*
	63	* GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
	64	* [3:2] = FIFOWR index, [1:0] = FIFORD index
	65	*/
	66	GPIFWFSELECT = (0x3 << 6) \| (0x2 << 4) \| (0x1 << 2) \| (0x0 << 0);
	67
	68	/* Contains RDY* pin values. Read-only according to TRM. */
	69	GPIFREADYSTAT = 0;
1e588d06	70
c7e02d8c	71	/* Make GPIF stop on transaction count not flag. */
1e588d06	72	EP2GPIFPFSTOP = (0 << 0);
e41576ec JH	73	}
e41576ec JH	74
e41576ec JH	75	static void gpif_init_addr_pins(void)
	76	{
	77	/*
	78	* Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
	79	* PORTC[7:0] and PORTE[7]), and output an initial address (zero).
	80	* TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
	81	*/
	82	PORTCCFG = 0xff; /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
	83	OEC = 0xff; /* Configure PORTC[7:0] as outputs. */
	84	PORTECFG \|= 0x80; /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
	85	OEE \|= 0x80; /* Configure PORTE[7] as output. */
	86	SYNCDELAY();
	87	GPIFADRL = 0x00; /* Clear GPIFADR[7:0]. */
	88	SYNCDELAY();
	89	GPIFADRH = 0x00; /* Clear GPIFADR[8]. */
	90	}
	91
	92	static void gpif_init_flowstates(void)
	93	{
	94	/* Clear all flowstate registers, we don't use this functionality. */
	95	FLOWSTATE = 0;
	96	FLOWLOGIC = 0;
	97	FLOWEQ0CTL = 0;
	98	FLOWEQ1CTL = 0;
	99	FLOWHOLDOFF = 0;
	100	FLOWSTB = 0;
	101	FLOWSTBEDGE = 0;
	102	FLOWSTBHPERIOD = 0;
	103	}
	104
	105	void gpif_init_la(void)
	106	{
	107	/*
	108	* Setup the FX2 in GPIF master mode, using the internal clock
	109	* (non-inverted) at 48MHz, and using async sampling.
	110	*/
	111	IFCONFIG = 0xee;
	112
	113	/* Abort currently executing GPIF waveform (if any). */
	114	GPIFABORT = 0xff;
	115
	116	/* Setup the GPIF registers. */
	117	gpif_setup_registers();
	118
421e7d6d JH	119	/* Reset WAVEDATA. */
421e7d6d JH	120	gpif_reset_waveforms();
e41576ec JH	121
	122	/* Initialize GPIF address pins, output initial values. */
	123	gpif_init_addr_pins();
	124
	125	/* Initialize flowstate registers (not used by us). */
	126	gpif_init_flowstates();
293d7e9e	127
c7e02d8c	128	/* Reset the status. */
293d7e9e	129	gpif_acquiring = FALSE;
e41576ec JH	130	}
e41576ec JH	131
41e02f65	132	static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay, uint8_t output)
e41576ec	133	{
cd29817d UH	134	/*
cd29817d UH	135	* DELAY
baecf744 JH	136	* Delay cmd->sample_delay clocks.
baecf744 JH	137	*/
7dfad4cb	138	pSTATE[0] = delay;
baecf744	139
cd29817d UH	140	/*
cd29817d UH	141	* OPCODE
a371bdee	142	* SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
baecf744	143	*/
41e02f65	144	pSTATE[8] = 0;
baecf744	145
cd29817d UH	146	/*
cd29817d UH	147	* OUTPUT
41e02f65	148	* CTL[0:5]=output
baecf744	149	*/
c7d1f48c	150	pSTATE[16] = output;
baecf744	151
cd29817d UH	152	/*
	153	* LOGIC FUNCTION
	154	* Not used.
baecf744	155	*/
421e7d6d	156	pSTATE[24] = 0x00;
7dfad4cb	157	}
421e7d6d	158
10bb1488	159	static void gpif_make_data_dp_state(volatile BYTE *pSTATE)
7dfad4cb	160	{
cd29817d UH	161	/*
	162	* BRANCH
	163	* Branch to IDLE if condition is true, back to S0 otherwise.
baecf744 JH	164	*/
	165	pSTATE[0] = (7 << 3) \| (0 << 0);
	166
cd29817d UH	167	/*
cd29817d UH	168	* OPCODE
a371bdee	169	* SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1
baecf744	170	*/
a371bdee	171	pSTATE[8] = (1 << 1) \| (1 << 0);
baecf744	172
cd29817d UH	173	/*
cd29817d UH	174	* OUTPUT
41e02f65	175	* CTL[0:5]=0
baecf744	176	*/
421e7d6d	177	pSTATE[16] = 0x00;
baecf744	178
cd29817d UH	179	/*
cd29817d UH	180	* LOGIC FUNCTION
baecf744 JH	181	* Evaluate if the FIFO full flag is set.
	182	* LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
	183	*/
	184	pSTATE[24] = (6 << 3) \| (6 << 0);
7dfad4cb JH	185	}
7dfad4cb JH	186
fb08a72d	187	bool gpif_acquisition_start(const struct cmd_start_acquisition *cmd)
7dfad4cb	188	{
fb08a72d JH	189	int i;
fb08a72d JH	190	volatile BYTE *pSTATE = &GPIF_WAVE_DATA;
7dfad4cb JH	191
	192	/* Ensure GPIF is idle before reconfiguration. */
	193	while (!(GPIFTRIG & 0x80));
	194
5d492e18	195	/* Configure the EP2 FIFO. */
6aa5d1f4	196	if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT)
daf6d940	197	EP2FIFOCFG = bmAUTOIN \| bmWORDWIDE;
6aa5d1f4	198	else
daf6d940	199	EP2FIFOCFG = bmAUTOIN;
daf6d940 JH	200	SYNCDELAY();
daf6d940 JH	201
7dfad4cb JH	202	/* Set IFCONFIG to the correct clock source. */
	203	if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
	204	IFCONFIG = bmIFCLKSRC \| bm3048MHZ \| bmIFCLKOE \| bmASYNC \|
	205	bmGSTATE \| bmIFGPIF;
	206	} else {
	207	IFCONFIG = bmIFCLKSRC \| bmIFCLKOE \| bmASYNC \|
	208	bmGSTATE \| bmIFGPIF;
	209	}
	210
6aa5d1f4	211	/* Populate delay states. */
b93872aa PF	212	if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) \|\|
	213	cmd->sample_delay_h >= 6)
	214	return false;
	215
8f87f877	216	if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
b93872aa	217	uint8_t delay_1, delay_2 = cmd->sample_delay_l;
7dfad4cb	218
6aa5d1f4	219	/* We need a pulse where the CTL1/2 pins alternate states. */
b93872aa PF	220	if (cmd->sample_delay_h) {
	221	for (i = 0; i < cmd->sample_delay_h; i++)
	222	gpif_make_delay_state(pSTATE++, 0, 0x06);
	223	} else {
	224	delay_1 = delay_2 / 2;
	225	delay_2 -= delay_1;
	226	gpif_make_delay_state(pSTATE++, delay_1, 0x06);
	227	}
	228
6aa5d1f4	229	/* sample_delay_l is always != 0 for the supported rates. */
1f99664c	230	gpif_make_delay_state(pSTATE++, delay_2, 0x00);
8f87f877	231	} else {
8f87f877	232	for (i = 0; i < cmd->sample_delay_h; i++)
41e02f65	233	gpif_make_delay_state(pSTATE++, 0, 0x00);
8f87f877 BL	234
8f87f877 BL	235	if (cmd->sample_delay_l != 0)
41e02f65	236	gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00);
8f87f877	237	}
7dfad4cb JH	238
7dfad4cb JH	239	/* Populate S1 - the decision point. */
10bb1488	240	gpif_make_data_dp_state(pSTATE++);
421e7d6d	241
cd29817d	242	/* Execute the whole GPIF waveform once. */
1e588d06 JH	243	gpif_set_tc16(1);
1e588d06 JH	244
e41576ec JH	245	/* Perform the initial GPIF read. */
e41576ec JH	246	gpif_fifo_read(GPIF_EP2);
293d7e9e	247
cd29817d	248	/* Update the status. */
293d7e9e	249	gpif_acquiring = TRUE;
fb08a72d JH	250
fb08a72d JH	251	return true;
293d7e9e JH	252	}
	253
	254	void gpif_poll(void)
	255	{
cd29817d UH	256	/* Detect if acquisition has completed. */
	257	if (gpif_acquiring && (GPIFTRIG & 0x80)) {
	258	/* Activate NAK-ALL to avoid race conditions. */
293d7e9e JH	259	FIFORESET = 0x80;
	260	SYNCDELAY();
	261
cd29817d	262	/* Switch to manual mode. */
293d7e9e JH	263	EP2FIFOCFG = 0;
	264	SYNCDELAY();
	265
cd29817d	266	/* Reset EP2. */
293d7e9e JH	267	FIFORESET = 0x02;
	268	SYNCDELAY();
	269
cd29817d	270	/* Return to auto mode. */
293d7e9e JH	271	EP2FIFOCFG = bmAUTOIN;
	272	SYNCDELAY();
	273
cd29817d	274	/* Release NAK-ALL. */
293d7e9e JH	275	FIFORESET = 0x00;
	276	SYNCDELAY();
	277
	278	gpif_acquiring = FALSE;
	279	}
e41576ec	280	}