[sigrok-firmware-fx2lafw.git] / gpif-acquisition.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#include <eputils.h>
#include <fx2regs.h>
#include <fx2macros.h>
#include <delay.h>
#include <gpif.h>
#include <fx2lafw.h>
#include <gpif-acquisition.h>

__bit gpif_acquiring;

static void gpif_reset_waveforms(void)
{
	int i;

	/* Reset WAVEDATA. */
	AUTOPTRSETUP = 0x03;
	AUTOPTRH1 = 0xe4;
	AUTOPTRL1 = 0x00;
	for (i = 0; i < 128; i++)
		EXTAUTODAT1 = 0;
}

static void gpif_setup_registers(void)
{
	/* TODO. Value probably irrelevant, as we don't use RDY* signals? */
	GPIFREADYCFG = 0;

	/*
	 * Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs.
	 * TODO: Probably irrelevant, as we don't use CTL0-CTL5?
	 */
	GPIFCTLCFG = 0;

	/* When GPIF is idle, tri-state the data bus. */
	/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
	GPIFIDLECS = (0 << 0);

	/* When GPIF is idle, set CTL0-CTL5 to 0. */
	GPIFIDLECTL = 0;

	/*
	 * Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
	 * but not used by us.
	 *
	 * GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
	 *               [3:2] = FIFOWR index, [1:0] = FIFORD index
	 */
	GPIFWFSELECT = (0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0);

	/* Contains RDY* pin values. Read-only according to TRM. */
	GPIFREADYSTAT = 0;

	/* Make GPIF stop on transaction count not flag. */
	EP2GPIFPFSTOP = (0 << 0);
}

static void gpif_init_addr_pins(void)
{
	/*
	 * Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
	 * PORTC[7:0] and PORTE[7]), and output an initial address (zero).
	 * TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
	 */
	PORTCCFG = 0xff;    /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
	OEC = 0xff;         /* Configure PORTC[7:0] as outputs. */
	PORTECFG |= 0x80;   /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
	OEE |= 0x80;        /* Configure PORTE[7] as output. */
	SYNCDELAY();
	GPIFADRL = 0x00;    /* Clear GPIFADR[7:0]. */
	SYNCDELAY();
	GPIFADRH = 0x00;    /* Clear GPIFADR[8]. */
}

static void gpif_init_flowstates(void)
{
	/* Clear all flowstate registers, we don't use this functionality. */
	FLOWSTATE = 0;
	FLOWLOGIC = 0;
	FLOWEQ0CTL = 0;
	FLOWEQ1CTL = 0;
	FLOWHOLDOFF = 0;
	FLOWSTB = 0;
	FLOWSTBEDGE = 0;
	FLOWSTBHPERIOD = 0;
}

void gpif_init_la(void)
{
	/*
	 * Setup the FX2 in GPIF master mode, using the internal clock
	 * (non-inverted) at 48MHz, and using async sampling.
	 */
	IFCONFIG = 0xee;

	/* Abort currently executing GPIF waveform (if any). */
	GPIFABORT = 0xff;

	/* Setup the GPIF registers. */
	gpif_setup_registers();

	/* Reset WAVEDATA. */
	gpif_reset_waveforms();

	/* Initialize GPIF address pins, output initial values. */
	gpif_init_addr_pins();

	/* Initialize flowstate registers (not used by us). */
	gpif_init_flowstates();

	/* Reset the status. */
	gpif_acquiring = FALSE;
}

static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay, uint8_t output)
{
	/*
	 * DELAY
	 * Delay cmd->sample_delay clocks.
	 */
	pSTATE[0] = delay;

	/*
	 * OPCODE
	 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
	 */
	pSTATE[8] = 0;

	/*
	 * OUTPUT
	 * CTL[0:5]=output
	 */
	pSTATE[16] = output;

	/*
	 * LOGIC FUNCTION
	 * Not used.
	 */
	pSTATE[24] = 0x00;
}

static void gpif_make_data_dp_state(volatile BYTE *pSTATE)
{
	/*
	 * BRANCH
	 * Branch to IDLE if condition is true, back to S0 otherwise.
	 */
	pSTATE[0] = (7 << 3) | (0 << 0);

	/*
	 * OPCODE
	 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1
	 */
	pSTATE[8] = (1 << 1) | (1 << 0);

	/*
	 * OUTPUT
	 * CTL[0:5]=0
	 */
	pSTATE[16] = 0x00;

	/*
	 * LOGIC FUNCTION
	 * Evaluate if the FIFO full flag is set.
	 * LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
	 */
	pSTATE[24] = (6 << 3) | (6 << 0);
}

bool gpif_acquisition_start(const struct cmd_start_acquisition *cmd)
{
	int i;
	volatile BYTE *pSTATE = &GPIF_WAVE_DATA;

	/* Ensure GPIF is idle before reconfiguration. */
	while (!(GPIFTRIG & 0x80));

	/* Configure the EP2 FIFO. */
	if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT) {
		EP2FIFOCFG = bmAUTOIN | bmWORDWIDE;
	} else {
		EP2FIFOCFG = bmAUTOIN;
	}
	SYNCDELAY();

	/* Set IFCONFIG to the correct clock source. */
	if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
		IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmASYNC |
			   bmGSTATE | bmIFGPIF;
	} else {
		IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC |
			   bmGSTATE | bmIFGPIF;
	}

	if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
		uint8_t delay_1, delay_2;

		/* We need a pulse where the CTL2 pin alternates states. */

		/* Make the low pulse shorter then the high pulse. */
		delay_2 = cmd->sample_delay_l >> 2;
		/* Work around >12MHz case resulting in a 0 delay low pulse. */
		if (delay_2 == 0)
			delay_2 = 1;
		delay_1 = cmd->sample_delay_l - delay_2;

		gpif_make_delay_state(pSTATE++, delay_2, 0x40);
		gpif_make_delay_state(pSTATE++, delay_1, 0x46);
	} else {
		/* Populate delay states. */
		if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) ||
			cmd->sample_delay_h >= 6)
			return false;

		for (i = 0; i < cmd->sample_delay_h; i++)
			gpif_make_delay_state(pSTATE++, 0, 0x00);

		if (cmd->sample_delay_l != 0)
			gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00);
	}

	/* Populate S1 - the decision point. */
	gpif_make_data_dp_state(pSTATE++);

	/* Execute the whole GPIF waveform once. */
	gpif_set_tc16(1);

	/* Perform the initial GPIF read. */
	gpif_fifo_read(GPIF_EP2);

	/* Update the status. */
	gpif_acquiring = TRUE;

	return true;
}

void gpif_poll(void)
{
	/* Detect if acquisition has completed. */
	if (gpif_acquiring && (GPIFTRIG & 0x80)) {
		/* Activate NAK-ALL to avoid race conditions. */
		FIFORESET = 0x80;
		SYNCDELAY();

		/* Switch to manual mode. */
		EP2FIFOCFG = 0;
		SYNCDELAY();

		/* Reset EP2. */
		FIFORESET = 0x02;
		SYNCDELAY();

		/* Return to auto mode. */
		EP2FIFOCFG = bmAUTOIN;
		SYNCDELAY();

		/* Release NAK-ALL. */
		FIFORESET = 0x00;
		SYNCDELAY();

		gpif_acquiring = FALSE;
	}
}
Commit	Line	Data
e41576ec	1	/*
a986cfff	2	* This file is part of the sigrok-firmware-fx2lafw project.
e41576ec JH	3	*
	4	* Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	*/
	21
293d7e9e	22	#include <eputils.h>
e41576ec JH	23	#include <fx2regs.h>
	24	#include <fx2macros.h>
	25	#include <delay.h>
	26	#include <gpif.h>
e41576ec JH	27	#include <fx2lafw.h>
	28	#include <gpif-acquisition.h>
	29
8819f75c	30	__bit gpif_acquiring;
293d7e9e	31
421e7d6d JH	32	static void gpif_reset_waveforms(void)
	33	{
	34	int i;
e41576ec	35
421e7d6d JH	36	/* Reset WAVEDATA. */
	37	AUTOPTRSETUP = 0x03;
	38	AUTOPTRH1 = 0xe4;
	39	AUTOPTRL1 = 0x00;
	40	for (i = 0; i < 128; i++)
	41	EXTAUTODAT1 = 0;
	42	}
e41576ec JH	43
	44	static void gpif_setup_registers(void)
	45	{
	46	/* TODO. Value probably irrelevant, as we don't use RDY* signals? */
	47	GPIFREADYCFG = 0;
	48
	49	/*
	50	* Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs.
	51	* TODO: Probably irrelevant, as we don't use CTL0-CTL5?
	52	*/
	53	GPIFCTLCFG = 0;
	54
	55	/* When GPIF is idle, tri-state the data bus. */
	56	/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
6398a519	57	GPIFIDLECS = (0 << 0);
e41576ec JH	58
	59	/* When GPIF is idle, set CTL0-CTL5 to 0. */
	60	GPIFIDLECTL = 0;
	61
	62	/*
421e7d6d	63	* Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
e41576ec JH	64	* but not used by us.
	65	*
	66	* GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
	67	* [3:2] = FIFOWR index, [1:0] = FIFORD index
	68	*/
	69	GPIFWFSELECT = (0x3 << 6) \| (0x2 << 4) \| (0x1 << 2) \| (0x0 << 0);
	70
	71	/* Contains RDY* pin values. Read-only according to TRM. */
	72	GPIFREADYSTAT = 0;
1e588d06	73
c7e02d8c	74	/* Make GPIF stop on transaction count not flag. */
1e588d06	75	EP2GPIFPFSTOP = (0 << 0);
e41576ec JH	76	}
e41576ec JH	77
e41576ec JH	78	static void gpif_init_addr_pins(void)
	79	{
	80	/*
	81	* Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
	82	* PORTC[7:0] and PORTE[7]), and output an initial address (zero).
	83	* TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
	84	*/
	85	PORTCCFG = 0xff; /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
	86	OEC = 0xff; /* Configure PORTC[7:0] as outputs. */
	87	PORTECFG \|= 0x80; /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
	88	OEE \|= 0x80; /* Configure PORTE[7] as output. */
	89	SYNCDELAY();
	90	GPIFADRL = 0x00; /* Clear GPIFADR[7:0]. */
	91	SYNCDELAY();
	92	GPIFADRH = 0x00; /* Clear GPIFADR[8]. */
	93	}
	94
	95	static void gpif_init_flowstates(void)
	96	{
	97	/* Clear all flowstate registers, we don't use this functionality. */
	98	FLOWSTATE = 0;
	99	FLOWLOGIC = 0;
	100	FLOWEQ0CTL = 0;
	101	FLOWEQ1CTL = 0;
	102	FLOWHOLDOFF = 0;
	103	FLOWSTB = 0;
	104	FLOWSTBEDGE = 0;
	105	FLOWSTBHPERIOD = 0;
	106	}
	107
	108	void gpif_init_la(void)
	109	{
	110	/*
	111	* Setup the FX2 in GPIF master mode, using the internal clock
	112	* (non-inverted) at 48MHz, and using async sampling.
	113	*/
	114	IFCONFIG = 0xee;
	115
	116	/* Abort currently executing GPIF waveform (if any). */
	117	GPIFABORT = 0xff;
	118
	119	/* Setup the GPIF registers. */
	120	gpif_setup_registers();
	121
421e7d6d JH	122	/* Reset WAVEDATA. */
421e7d6d JH	123	gpif_reset_waveforms();
e41576ec JH	124
	125	/* Initialize GPIF address pins, output initial values. */
	126	gpif_init_addr_pins();
	127
	128	/* Initialize flowstate registers (not used by us). */
	129	gpif_init_flowstates();
293d7e9e	130
c7e02d8c	131	/* Reset the status. */
293d7e9e	132	gpif_acquiring = FALSE;
e41576ec JH	133	}
e41576ec JH	134
41e02f65	135	static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay, uint8_t output)
e41576ec	136	{
cd29817d UH	137	/*
cd29817d UH	138	* DELAY
baecf744 JH	139	* Delay cmd->sample_delay clocks.
baecf744 JH	140	*/
7dfad4cb	141	pSTATE[0] = delay;
baecf744	142
cd29817d UH	143	/*
cd29817d UH	144	* OPCODE
a371bdee	145	* SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
baecf744	146	*/
41e02f65	147	pSTATE[8] = 0;
baecf744	148
cd29817d UH	149	/*
cd29817d UH	150	* OUTPUT
41e02f65	151	* CTL[0:5]=output
baecf744	152	*/
c7d1f48c	153	pSTATE[16] = output;
baecf744	154
cd29817d UH	155	/*
	156	* LOGIC FUNCTION
	157	* Not used.
baecf744	158	*/
421e7d6d	159	pSTATE[24] = 0x00;
7dfad4cb	160	}
421e7d6d	161
10bb1488	162	static void gpif_make_data_dp_state(volatile BYTE *pSTATE)
7dfad4cb	163	{
cd29817d UH	164	/*
	165	* BRANCH
	166	* Branch to IDLE if condition is true, back to S0 otherwise.
baecf744 JH	167	*/
	168	pSTATE[0] = (7 << 3) \| (0 << 0);
	169
cd29817d UH	170	/*
cd29817d UH	171	* OPCODE
a371bdee	172	* SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1
baecf744	173	*/
a371bdee	174	pSTATE[8] = (1 << 1) \| (1 << 0);
baecf744	175
cd29817d UH	176	/*
cd29817d UH	177	* OUTPUT
41e02f65	178	* CTL[0:5]=0
baecf744	179	*/
421e7d6d	180	pSTATE[16] = 0x00;
baecf744	181
cd29817d UH	182	/*
cd29817d UH	183	* LOGIC FUNCTION
baecf744 JH	184	* Evaluate if the FIFO full flag is set.
	185	* LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
	186	*/
	187	pSTATE[24] = (6 << 3) \| (6 << 0);
7dfad4cb JH	188	}
7dfad4cb JH	189
fb08a72d	190	bool gpif_acquisition_start(const struct cmd_start_acquisition *cmd)
7dfad4cb	191	{
fb08a72d JH	192	int i;
fb08a72d JH	193	volatile BYTE *pSTATE = &GPIF_WAVE_DATA;
7dfad4cb JH	194
	195	/* Ensure GPIF is idle before reconfiguration. */
	196	while (!(GPIFTRIG & 0x80));
	197
5d492e18 UH	198	/* Configure the EP2 FIFO. */
5d492e18 UH	199	if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT) {
daf6d940 JH	200	EP2FIFOCFG = bmAUTOIN \| bmWORDWIDE;
	201	} else {
	202	EP2FIFOCFG = bmAUTOIN;
	203	}
	204	SYNCDELAY();
	205
7dfad4cb JH	206	/* Set IFCONFIG to the correct clock source. */
	207	if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
	208	IFCONFIG = bmIFCLKSRC \| bm3048MHZ \| bmIFCLKOE \| bmASYNC \|
	209	bmGSTATE \| bmIFGPIF;
	210	} else {
	211	IFCONFIG = bmIFCLKSRC \| bmIFCLKOE \| bmASYNC \|
	212	bmGSTATE \| bmIFGPIF;
	213	}
	214
8f87f877 BL	215	if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
8f87f877 BL	216	uint8_t delay_1, delay_2;
7dfad4cb	217
8f87f877	218	/* We need a pulse where the CTL2 pin alternates states. */
7dfad4cb	219
8f87f877 BL	220	/* Make the low pulse shorter then the high pulse. */
	221	delay_2 = cmd->sample_delay_l >> 2;
	222	/* Work around >12MHz case resulting in a 0 delay low pulse. */
	223	if (delay_2 == 0)
	224	delay_2 = 1;
	225	delay_1 = cmd->sample_delay_l - delay_2;
	226
41e02f65 PF	227	gpif_make_delay_state(pSTATE++, delay_2, 0x40);
41e02f65 PF	228	gpif_make_delay_state(pSTATE++, delay_1, 0x46);
8f87f877 BL	229	} else {
	230	/* Populate delay states. */
	231	if ((cmd->sample_delay_h == 0 && cmd->sample_delay_l == 0) \|\|
	232	cmd->sample_delay_h >= 6)
	233	return false;
	234
	235	for (i = 0; i < cmd->sample_delay_h; i++)
41e02f65	236	gpif_make_delay_state(pSTATE++, 0, 0x00);
8f87f877 BL	237
8f87f877 BL	238	if (cmd->sample_delay_l != 0)
41e02f65	239	gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00);
8f87f877	240	}
7dfad4cb JH	241
7dfad4cb JH	242	/* Populate S1 - the decision point. */
10bb1488	243	gpif_make_data_dp_state(pSTATE++);
421e7d6d	244
cd29817d	245	/* Execute the whole GPIF waveform once. */
1e588d06 JH	246	gpif_set_tc16(1);
1e588d06 JH	247
e41576ec JH	248	/* Perform the initial GPIF read. */
e41576ec JH	249	gpif_fifo_read(GPIF_EP2);
293d7e9e	250
cd29817d	251	/* Update the status. */
293d7e9e	252	gpif_acquiring = TRUE;
fb08a72d JH	253
fb08a72d JH	254	return true;
293d7e9e JH	255	}
	256
	257	void gpif_poll(void)
	258	{
cd29817d UH	259	/* Detect if acquisition has completed. */
	260	if (gpif_acquiring && (GPIFTRIG & 0x80)) {
	261	/* Activate NAK-ALL to avoid race conditions. */
293d7e9e JH	262	FIFORESET = 0x80;
	263	SYNCDELAY();
	264
cd29817d	265	/* Switch to manual mode. */
293d7e9e JH	266	EP2FIFOCFG = 0;
	267	SYNCDELAY();
	268
cd29817d	269	/* Reset EP2. */
293d7e9e JH	270	FIFORESET = 0x02;
	271	SYNCDELAY();
	272
cd29817d	273	/* Return to auto mode. */
293d7e9e JH	274	EP2FIFOCFG = bmAUTOIN;
	275	SYNCDELAY();
	276
cd29817d	277	/* Release NAK-ALL. */
293d7e9e JH	278	FIFORESET = 0x00;
	279	SYNCDELAY();
	280
	281	gpif_acquiring = FALSE;
	282	}
e41576ec	283	}