[sigrok-firmware-fx2lafw.git] / gpif-acquisition.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include <eputils.h>
#include <fx2regs.h>
#include <fx2macros.h>
#include <delay.h>
#include <gpif.h>
#include <fx2lafw.h>
#include <gpif-acquisition.h>

enum gpif_status gpif_acquiring = STOPPED;

static void gpif_reset_waveforms(void)
{
	int i;

	/* Reset WAVEDATA. */
	AUTOPTRSETUP = 0x03;
	AUTOPTRH1 = 0xe4;
	AUTOPTRL1 = 0x00;
	for (i = 0; i < 128; i++)
		EXTAUTODAT1 = 0;
}

static void gpif_setup_registers(void)
{
	/* TODO. Value probably irrelevant, as we don't use RDY* signals? */
	GPIFREADYCFG = 0;

	/* Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs. */
	GPIFCTLCFG = 0;

	/* When GPIF is idle, tri-state the data bus. */
	/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
	GPIFIDLECS = (0 << 0);

	/* When GPIF is idle, set CTL0-CTL5 to 0. */
	GPIFIDLECTL = 0;

	/*
	 * Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
	 * but not used by us.
	 *
	 * GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
	 *               [3:2] = FIFOWR index, [1:0] = FIFORD index
	 */
	GPIFWFSELECT = (0x3u << 6) | (0x2u << 4) | (0x1u << 2) | (0x0u << 0);

	/* Contains RDY* pin values. Read-only according to TRM. */
	GPIFREADYSTAT = 0;

	/* Make GPIF stop on transaction count not flag. */
	EP2GPIFPFSTOP = (0 << 0);
}

static void gpif_init_addr_pins(void)
{
	/*
	 * Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
	 * PORTC[7:0] and PORTE[7]), and output an initial address (zero).
	 * TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
	 */
	PORTCCFG = 0xff;    /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
	OEC = 0xff;         /* Configure PORTC[7:0] as outputs. */
	PORTECFG |= 0x80;   /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
	OEE |= 0x80;        /* Configure PORTE[7] as output. */
	SYNCDELAY();
	GPIFADRL = 0x00;    /* Clear GPIFADR[7:0]. */
	SYNCDELAY();
	GPIFADRH = 0x00;    /* Clear GPIFADR[8]. */
}

static void gpif_init_flowstates(void)
{
	/* Clear all flowstate registers, we don't use this functionality. */
	FLOWSTATE = 0;
	FLOWLOGIC = 0;
	FLOWEQ0CTL = 0;
	FLOWEQ1CTL = 0;
	FLOWHOLDOFF = 0;
	FLOWSTB = 0;
	FLOWSTBEDGE = 0;
	FLOWSTBHPERIOD = 0;
}

void gpif_init_la(void)
{
	/*
	 * Setup the FX2 in GPIF master mode, using the internal clock
	 * (non-inverted) at 48MHz, and using async sampling.
	 */
	IFCONFIG = 0xee;

	/* Abort currently executing GPIF waveform (if any). */
	GPIFABORT = 0xff;

	/* Setup the GPIF registers. */
	gpif_setup_registers();

	/* Reset WAVEDATA. */
	gpif_reset_waveforms();

	/* Initialize GPIF address pins, output initial values. */
	gpif_init_addr_pins();

	/* Initialize flowstate registers (not used by us). */
	gpif_init_flowstates();

	/* Reset the status. */
	gpif_acquiring = STOPPED;
}

static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay, uint8_t output)
{
	/*
	 * DELAY
	 * Delay cmd->sample_delay clocks.
	 */
	pSTATE[0] = delay;

	/*
	 * OPCODE
	 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
	 */
	pSTATE[8] = 0;

	/*
	 * OUTPUT
	 * CTL[0:5]=output
	 */
	pSTATE[16] = output;

	/*
	 * LOGIC FUNCTION
	 * Not used.
	 */
	pSTATE[24] = 0x00;
}

static void gpif_make_data_dp_state(volatile BYTE *pSTATE)
{
	/*
	 * BRANCH
	 * Branch to IDLE if condition is true, back to S0 otherwise.
	 */
	pSTATE[0] = (1u << 7) | (7u << 3) | (0u << 0);

	/*
	 * OPCODE
	 * SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1
	 */
	pSTATE[8] = (1 << 1) | (1 << 0);

	/*
	 * OUTPUT
	 * CTL[0:5]=0
	 */
	pSTATE[16] = 0x00;

	/*
	 * LOGIC FUNCTION
	 * Evaluate if the FIFO full flag is set.
	 * LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
	 */
	pSTATE[24] = (6 << 3) | (6 << 0);
}

bool gpif_acquisition_prepare(const struct cmd_start_acquisition *cmd)
{
	int i;
	volatile BYTE *pSTATE = &GPIF_WAVE_DATA;

	/* Ensure GPIF is idle before reconfiguration. */
	while (!(GPIFTRIG & 0x80));

	/* Configure the EP2 FIFO. */
	if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT)
		EP2FIFOCFG = bmAUTOIN | bmWORDWIDE;
	else
		EP2FIFOCFG = bmAUTOIN;
	SYNCDELAY();

	/* Set IFCONFIG to the correct clock source. */
	if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
		IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmASYNC |
			   bmGSTATE | bmIFGPIF;
	} else {
		IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC |
			   bmGSTATE | bmIFGPIF;
	}

	/* Populate delay states. */
	if (cmd->sample_delay_h >= 6)
		return false;

	if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
		uint8_t delay_1, delay_2 = cmd->sample_delay_l;

		/* We need a pulse where the CTL1/2 pins alternate states. */
		if (cmd->sample_delay_h) {
			for (i = 0; i < cmd->sample_delay_h; i++)
				gpif_make_delay_state(pSTATE++, 0, 0x06);
		} else {
			delay_1 = delay_2 / 2;
			delay_2 -= delay_1;
			gpif_make_delay_state(pSTATE++, delay_1, 0x06);
		}

		/* sample_delay_l is always != 0 for the supported rates. */
		gpif_make_delay_state(pSTATE++, delay_2, 0x00);
	} else {
		for (i = 0; i < cmd->sample_delay_h; i++)
			gpif_make_delay_state(pSTATE++, 0, 0x00);

		if (cmd->sample_delay_l != 0)
			gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00);
	}

	/* Populate S1 - the decision point. */
	gpif_make_data_dp_state(pSTATE++);

	/* Update the status. */
	gpif_acquiring = PREPARED;

	return true;
}

void gpif_acquisition_start(void)
{
	/* Execute the whole GPIF waveform once. */
	gpif_set_tc16(1);

	/* Perform the initial GPIF read. */
	gpif_fifo_read(GPIF_EP2);

	/* Update the status. */
	gpif_acquiring = RUNNING;
}

void gpif_poll(void)
{
	/* Detect if acquisition has completed. */
	if ((gpif_acquiring == RUNNING) && (GPIFTRIG & 0x80)) {
		/* Activate NAK-ALL to avoid race conditions. */
		FIFORESET = 0x80;
		SYNCDELAY();

		/* Switch to manual mode. */
		EP2FIFOCFG = 0;
		SYNCDELAY();

		/* Reset EP2. */
		FIFORESET = 0x02;
		SYNCDELAY();

		/* Return to auto mode. */
		EP2FIFOCFG = bmAUTOIN;
		SYNCDELAY();

		/* Release NAK-ALL. */
		FIFORESET = 0x00;
		SYNCDELAY();

		gpif_acquiring = STOPPED;
	}
}
Commit	Line	Data
e41576ec	1	/*
a986cfff	2	* This file is part of the sigrok-firmware-fx2lafw project.
e41576ec JH	3	*
	4	* Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
040a6eae	18	* along with this program; if not, see <http://www.gnu.org/licenses/>.
e41576ec JH	19	*/
e41576ec JH	20
293d7e9e	21	#include <eputils.h>
e41576ec JH	22	#include <fx2regs.h>
	23	#include <fx2macros.h>
	24	#include <delay.h>
	25	#include <gpif.h>
e41576ec JH	26	#include <fx2lafw.h>
	27	#include <gpif-acquisition.h>
	28
cfeb1a36	29	enum gpif_status gpif_acquiring = STOPPED;
293d7e9e	30
421e7d6d JH	31	static void gpif_reset_waveforms(void)
	32	{
	33	int i;
e41576ec	34
421e7d6d JH	35	/* Reset WAVEDATA. */
	36	AUTOPTRSETUP = 0x03;
	37	AUTOPTRH1 = 0xe4;
	38	AUTOPTRL1 = 0x00;
	39	for (i = 0; i < 128; i++)
	40	EXTAUTODAT1 = 0;
	41	}
e41576ec JH	42
	43	static void gpif_setup_registers(void)
	44	{
	45	/* TODO. Value probably irrelevant, as we don't use RDY* signals? */
	46	GPIFREADYCFG = 0;
	47
6aa5d1f4	48	/* Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs. */
e41576ec JH	49	GPIFCTLCFG = 0;
	50
	51	/* When GPIF is idle, tri-state the data bus. */
	52	/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
6398a519	53	GPIFIDLECS = (0 << 0);
e41576ec JH	54
	55	/* When GPIF is idle, set CTL0-CTL5 to 0. */
	56	GPIFIDLECTL = 0;
	57
	58	/*
421e7d6d	59	* Map index 0 in WAVEDATA to FIFORD. The rest is assigned too,
e41576ec JH	60	* but not used by us.
	61	*
	62	* GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
	63	* [3:2] = FIFOWR index, [1:0] = FIFORD index
	64	*/
f6ef2ff7	65	GPIFWFSELECT = (0x3u << 6) \| (0x2u << 4) \| (0x1u << 2) \| (0x0u << 0);
e41576ec JH	66
	67	/* Contains RDY* pin values. Read-only according to TRM. */
	68	GPIFREADYSTAT = 0;
1e588d06	69
c7e02d8c	70	/* Make GPIF stop on transaction count not flag. */
1e588d06	71	EP2GPIFPFSTOP = (0 << 0);
e41576ec JH	72	}
e41576ec JH	73
e41576ec JH	74	static void gpif_init_addr_pins(void)
	75	{
	76	/*
	77	* Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
	78	* PORTC[7:0] and PORTE[7]), and output an initial address (zero).
	79	* TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
	80	*/
	81	PORTCCFG = 0xff; /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
	82	OEC = 0xff; /* Configure PORTC[7:0] as outputs. */
	83	PORTECFG \|= 0x80; /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
	84	OEE \|= 0x80; /* Configure PORTE[7] as output. */
	85	SYNCDELAY();
	86	GPIFADRL = 0x00; /* Clear GPIFADR[7:0]. */
	87	SYNCDELAY();
	88	GPIFADRH = 0x00; /* Clear GPIFADR[8]. */
	89	}
	90
	91	static void gpif_init_flowstates(void)
	92	{
	93	/* Clear all flowstate registers, we don't use this functionality. */
	94	FLOWSTATE = 0;
	95	FLOWLOGIC = 0;
	96	FLOWEQ0CTL = 0;
	97	FLOWEQ1CTL = 0;
	98	FLOWHOLDOFF = 0;
	99	FLOWSTB = 0;
	100	FLOWSTBEDGE = 0;
	101	FLOWSTBHPERIOD = 0;
	102	}
	103
	104	void gpif_init_la(void)
	105	{
	106	/*
	107	* Setup the FX2 in GPIF master mode, using the internal clock
	108	* (non-inverted) at 48MHz, and using async sampling.
	109	*/
	110	IFCONFIG = 0xee;
	111
	112	/* Abort currently executing GPIF waveform (if any). */
	113	GPIFABORT = 0xff;
	114
	115	/* Setup the GPIF registers. */
	116	gpif_setup_registers();
	117
421e7d6d JH	118	/* Reset WAVEDATA. */
421e7d6d JH	119	gpif_reset_waveforms();
e41576ec JH	120
	121	/* Initialize GPIF address pins, output initial values. */
	122	gpif_init_addr_pins();
	123
	124	/* Initialize flowstate registers (not used by us). */
	125	gpif_init_flowstates();
293d7e9e	126
c7e02d8c	127	/* Reset the status. */
cfeb1a36	128	gpif_acquiring = STOPPED;
e41576ec JH	129	}
e41576ec JH	130
41e02f65	131	static void gpif_make_delay_state(volatile BYTE *pSTATE, uint8_t delay, uint8_t output)
e41576ec	132	{
cd29817d UH	133	/*
cd29817d UH	134	* DELAY
baecf744 JH	135	* Delay cmd->sample_delay clocks.
baecf744 JH	136	*/
7dfad4cb	137	pSTATE[0] = delay;
baecf744	138
cd29817d UH	139	/*
cd29817d UH	140	* OPCODE
a371bdee	141	* SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=0, DP=0
baecf744	142	*/
41e02f65	143	pSTATE[8] = 0;
baecf744	144
cd29817d UH	145	/*
cd29817d UH	146	* OUTPUT
41e02f65	147	* CTL[0:5]=output
baecf744	148	*/
c7d1f48c	149	pSTATE[16] = output;
baecf744	150
cd29817d UH	151	/*
	152	* LOGIC FUNCTION
	153	* Not used.
baecf744	154	*/
421e7d6d	155	pSTATE[24] = 0x00;
7dfad4cb	156	}
421e7d6d	157
10bb1488	158	static void gpif_make_data_dp_state(volatile BYTE *pSTATE)
7dfad4cb	159	{
cd29817d UH	160	/*
	161	* BRANCH
	162	* Branch to IDLE if condition is true, back to S0 otherwise.
baecf744	163	*/
61f1c8fc	164	pSTATE[0] = (1u << 7) \| (7u << 3) \| (0u << 0);
baecf744	165
cd29817d UH	166	/*
cd29817d UH	167	* OPCODE
a371bdee	168	* SGL=0, GIN=0, INCAD=0, NEXT=0, DATA=1, DP=1
baecf744	169	*/
a371bdee	170	pSTATE[8] = (1 << 1) \| (1 << 0);
baecf744	171
cd29817d UH	172	/*
cd29817d UH	173	* OUTPUT
41e02f65	174	* CTL[0:5]=0
baecf744	175	*/
421e7d6d	176	pSTATE[16] = 0x00;
baecf744	177
cd29817d UH	178	/*
cd29817d UH	179	* LOGIC FUNCTION
baecf744 JH	180	* Evaluate if the FIFO full flag is set.
	181	* LFUNC=0 (AND), TERMA=6 (FIFO Flag), TERMB=6 (FIFO Flag)
	182	*/
	183	pSTATE[24] = (6 << 3) \| (6 << 0);
7dfad4cb JH	184	}
7dfad4cb JH	185
cfeb1a36	186	bool gpif_acquisition_prepare(const struct cmd_start_acquisition *cmd)
7dfad4cb	187	{
fb08a72d JH	188	int i;
fb08a72d JH	189	volatile BYTE *pSTATE = &GPIF_WAVE_DATA;
7dfad4cb JH	190
	191	/* Ensure GPIF is idle before reconfiguration. */
	192	while (!(GPIFTRIG & 0x80));
	193
5d492e18	194	/* Configure the EP2 FIFO. */
6aa5d1f4	195	if (cmd->flags & CMD_START_FLAGS_SAMPLE_16BIT)
daf6d940	196	EP2FIFOCFG = bmAUTOIN \| bmWORDWIDE;
6aa5d1f4	197	else
daf6d940	198	EP2FIFOCFG = bmAUTOIN;
daf6d940 JH	199	SYNCDELAY();
daf6d940 JH	200
7dfad4cb JH	201	/* Set IFCONFIG to the correct clock source. */
	202	if (cmd->flags & CMD_START_FLAGS_CLK_48MHZ) {
	203	IFCONFIG = bmIFCLKSRC \| bm3048MHZ \| bmIFCLKOE \| bmASYNC \|
	204	bmGSTATE \| bmIFGPIF;
	205	} else {
	206	IFCONFIG = bmIFCLKSRC \| bmIFCLKOE \| bmASYNC \|
	207	bmGSTATE \| bmIFGPIF;
	208	}
	209
6aa5d1f4	210	/* Populate delay states. */
b283ba83	211	if (cmd->sample_delay_h >= 6)
b93872aa PF	212	return false;
b93872aa PF	213
8f87f877	214	if (cmd->flags & CMD_START_FLAGS_CLK_CTL2) {
b93872aa	215	uint8_t delay_1, delay_2 = cmd->sample_delay_l;
7dfad4cb	216
6aa5d1f4	217	/* We need a pulse where the CTL1/2 pins alternate states. */
b93872aa PF	218	if (cmd->sample_delay_h) {
	219	for (i = 0; i < cmd->sample_delay_h; i++)
	220	gpif_make_delay_state(pSTATE++, 0, 0x06);
	221	} else {
	222	delay_1 = delay_2 / 2;
	223	delay_2 -= delay_1;
	224	gpif_make_delay_state(pSTATE++, delay_1, 0x06);
	225	}
	226
6aa5d1f4	227	/* sample_delay_l is always != 0 for the supported rates. */
1f99664c	228	gpif_make_delay_state(pSTATE++, delay_2, 0x00);
8f87f877	229	} else {
8f87f877	230	for (i = 0; i < cmd->sample_delay_h; i++)
41e02f65	231	gpif_make_delay_state(pSTATE++, 0, 0x00);
8f87f877 BL	232
8f87f877 BL	233	if (cmd->sample_delay_l != 0)
41e02f65	234	gpif_make_delay_state(pSTATE++, cmd->sample_delay_l, 0x00);
8f87f877	235	}
7dfad4cb JH	236
7dfad4cb JH	237	/* Populate S1 - the decision point. */
10bb1488	238	gpif_make_data_dp_state(pSTATE++);
421e7d6d	239
cfeb1a36 SB	240	/* Update the status. */
	241	gpif_acquiring = PREPARED;
	242
	243	return true;
	244	}
	245
	246	void gpif_acquisition_start(void)
	247	{
cd29817d	248	/* Execute the whole GPIF waveform once. */
1e588d06 JH	249	gpif_set_tc16(1);
1e588d06 JH	250
e41576ec JH	251	/* Perform the initial GPIF read. */
e41576ec JH	252	gpif_fifo_read(GPIF_EP2);
293d7e9e	253
cd29817d	254	/* Update the status. */
cfeb1a36	255	gpif_acquiring = RUNNING;
293d7e9e JH	256	}
	257
	258	void gpif_poll(void)
	259	{
cd29817d	260	/* Detect if acquisition has completed. */
cfeb1a36	261	if ((gpif_acquiring == RUNNING) && (GPIFTRIG & 0x80)) {
cd29817d	262	/* Activate NAK-ALL to avoid race conditions. */
293d7e9e JH	263	FIFORESET = 0x80;
	264	SYNCDELAY();
	265
cd29817d	266	/* Switch to manual mode. */
293d7e9e JH	267	EP2FIFOCFG = 0;
	268	SYNCDELAY();
	269
cd29817d	270	/* Reset EP2. */
293d7e9e JH	271	FIFORESET = 0x02;
	272	SYNCDELAY();
	273
cd29817d	274	/* Return to auto mode. */
293d7e9e JH	275	EP2FIFOCFG = bmAUTOIN;
	276	SYNCDELAY();
	277
cd29817d	278	/* Release NAK-ALL. */
293d7e9e JH	279	FIFORESET = 0x00;
	280	SYNCDELAY();
	281
cfeb1a36	282	gpif_acquiring = STOPPED;
293d7e9e	283	}
e41576ec	284	}