projects / sigrok-dumps.git / blame
| Commit | Line | Data |
|---|---|---|
| bfe7c799 BW |
1 | ------------------------------------------------------------------------------- |
| 2 | Brainchild IO-16DO Modbus communication | |
| 3 | ------------------------------------------------------------------------------- | |
| 4 | ||
| 5 | This is a dump of Modbus data from a Brainchild IO-16DO module. | |
| 6 | ||
| 7 | It was connected to a PC using a Prolific USB-RS232 converter and a cheap | |
| 8 | Chinese RS232-RS485 converter. | |
| 9 | ||
| 10 | Details: | |
| 11 | http://www.brainchild.com.tw/en/2_1752_41579/product/16_digital_outputs_id147280.html | |
| 12 | ||
| 13 | ||
| 14 | Logic analyzer setup | |
| 15 | -------------------- | |
| 16 | ||
| 17 | The logic analyzer used was a Saleae Logic16 clone (at 1MHz). | |
| 18 | ||
| 19 | It was connected on the RS232 line. | |
| 20 | The probes were connected through 10K resistors. | |
| 21 | ||
| 22 | Probe UART | |
| 23 | ---------------- | |
| 24 | 0 RX | |
| 25 | 1 TX | |
| 26 | ||
| 27 | ||
| 28 | Data | |
| 29 | ---- | |
| 30 | ||
| 31 | The sigrok command line used was: | |
| 32 | ||
| 33 | sigrok-cli -C 0,1 -c "samplerate=1 MHz" -d saleae-logic16 -o \ | |
| 34 | brainchild-io-16do.sr --time 300ms | |
| 35 | ||
| 36 | The requests were sent with the included brainchild-io-16do-activity.py script. | |
| 37 |