[sigrok-dumps.git] / spi / mrf24j40 / ecg / README

-------------------------------------------------------------------------------
Microchip MRF24J40MA
-------------------------------------------------------------------------------

This is a set of captures of the communication of an ECG device using a
Microchip MRF24J40MA RF chip.


Logic analyzer setup
--------------------

The logic analyzer used was a Saleae Logic (at 12MHz).

  Probe  MRF24J40MA
  -----------------
  0      CS#
  1      SDO (MISO)
  2      RESET#
  3      WAKE
  4      INT
  5      SDI (MOSI)
  6      SCK
  7      CONTROL2 (custom debug signal)


mrf24j40ma_no_txfails.sr
------------------------

This is a capture of a device where there aren't many TX fails (but some
occasional retries).


mrf24j40ma_many_txfails.sr
--------------------------

This is a capture of another device, where there are many TX fails and retries.
Commit	Line	Data
4844307d UH	1	-------------------------------------------------------------------------------
	2	Microchip MRF24J40MA
	3	-------------------------------------------------------------------------------
	4
	5	This is a set of captures of the communication of an ECG device using a
	6	Microchip MRF24J40MA RF chip.
	7
	8
	9	Logic analyzer setup
	10	--------------------
	11
	12	The logic analyzer used was a Saleae Logic (at 12MHz).
	13
	14	Probe MRF24J40MA
	15	-----------------
	16	0 CS#
	17	1 SDO (MISO)
	18	2 RESET#
	19	3 WAKE
	20	4 INT
	21	5 SDI (MOSI)
	22	6 SCK
	23	7 CONTROL2 (custom debug signal)
	24
	25
	26	mrf24j40ma_no_txfails.sr
	27	------------------------
	28
	29	This is a capture of a device where there aren't many TX fails (but some
	30	occasional retries).
	31
	32
	33	mrf24j40ma_many_txfails.sr
	34	--------------------------
	35
	36	This is a capture of another device, where there are many TX fails and retries.