Rename 'probe' to 'channel' everywhere.

[libsigrokdecode.git] / decoders / z80 / pd.py

diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py
index f07b76c931e6ad6ed28ca9d1d64b496ae9115ff8..299a20ec72496cc8ee27eb7b965ab0d85ff8d72d 100644 (file)
--- a/decoders/z80/pd.py
+++ b/decoders/z80/pd.py
@@ -56,7 +56,7 @@ ann_data_cycle_map = {
 
 def reduce_bus(bus):
     if 0xFF in bus:
-        return None # unassigned bus probes
+        return None # unassigned bus channels
     else:
         return reduce(lambda a, b: (a << 1) | b, reversed(bus))
 
@@ -69,10 +69,10 @@ class Decoder(srd.Decoder):
     name     = 'Z80'
     longname = 'Zilog Z80 CPU'
     desc     = 'Zilog Z80 microprocessor disassembly.'
-    license  = 'gplv2+'
+    license  = 'gplv3+'
     inputs   = ['logic']
     outputs  = ['z80']
-    probes = tuple({
+    channels = tuple({
             'id': 'd%d' % i,
             'name': 'D%d' % i,
             'desc': 'Data bus line %d' % i
@@ -82,7 +82,7 @@ class Decoder(srd.Decoder):
         {'id': 'rd', 'name': '/RD', 'desc': 'Memory or I/O read'},
         {'id': 'wr', 'name': '/WR', 'desc': 'Memory or I/O write'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'mreq', 'name': '/MREQ', 'desc': 'Memory request'},
         {'id': 'iorq', 'name': '/IORQ', 'desc': 'I/O request'},
     ) + tuple({