self.oldsym = 'J' # The "idle" state is J.
self.ss_block = None
self.samplenum = 0
- self.syms = []
self.bitrate = None
self.bitwidth = None
self.samplepos = None
self.samplenum_target = None
self.samplenum_edge = None
+ self.samplenum_lastedge = 0
self.oldpins = None
self.edgepins = None
self.consecutive_ones = 0
self.samplerate = value
self.bitrate = bitrates[self.options['signalling']]
self.bitwidth = float(self.samplerate) / float(self.bitrate)
- self.halfbit = int(self.bitwidth / 2)
def putpx(self, data):
- self.put(self.samplenum, self.samplenum, self.out_python, data)
+ s = self.samplenum_edge
+ self.put(s, s, self.out_python, data)
def putx(self, data):
- self.put(self.samplenum, self.samplenum, self.out_ann, data)
+ s = self.samplenum_edge
+ self.put(s, s, self.out_ann, data)
def putpm(self, data):
- s, h = self.samplenum, self.halfbit
- self.put(self.ss_block - h, s + h, self.out_python, data)
+ e = self.samplenum_edge
+ self.put(self.ss_block, e, self.out_python, data)
def putm(self, data):
- s, h = self.samplenum, self.halfbit
- self.put(self.ss_block - h, s + h, self.out_ann, data)
+ e = self.samplenum_edge
+ self.put(self.ss_block, e, self.out_ann, data)
def putpb(self, data):
- s, h = self.samplenum, self.halfbit
- self.put(self.samplenum_edge, s + h, self.out_python, data)
+ s, e = self.samplenum_lastedge, self.samplenum_edge
+ self.put(s, e, self.out_python, data)
def putb(self, data):
- s, h = self.samplenum, self.halfbit
- self.put(self.samplenum_edge, s + h, self.out_ann, data)
+ s, e = self.samplenum_lastedge, self.samplenum_edge
+ self.put(s, e, self.out_ann, data)
def set_new_target_samplenum(self):
self.samplepos += self.bitwidth;
self.samplenum_target = int(self.samplepos)
+ self.samplenum_lastedge = self.samplenum_edge
self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
def wait_for_sop(self, sym):
self.putx([4, ['SOP', 'S']])
self.state = 'GET BIT'
- def handle_bit(self, sym, b):
+ def handle_bit(self, b):
if self.consecutive_ones == 6:
if b == '0':
# Stuff bit.
def get_eop(self, sym):
# EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
- self.syms.append(sym)
+ self.set_new_target_samplenum()
self.putpb(['SYM', sym])
self.putb(sym_annotation[sym])
- self.set_new_target_samplenum()
self.oldsym = sym
- if self.syms[-2:] == ['SE0', 'J']:
+ if sym == 'SE0':
+ pass
+ elif sym == 'J':
# Got an EOP.
self.putpm(['EOP', None])
self.putm([5, ['EOP', 'E']])
- self.syms, self.state = [], 'IDLE'
+ self.state = 'IDLE'
self.bitwidth = float(self.samplerate) / float(self.bitrate)
+ else:
+ self.putpm(['ERR', None])
+ self.putm([8, ['EOP Error', 'EErr', 'E']])
+ self.state = 'IDLE'
def get_bit(self, sym):
+ self.set_new_target_samplenum()
if sym == 'SE0':
- # Start of an EOP. Change state, run get_eop() for this bit.
+ # Start of an EOP. Change state, save edge
self.state = 'GET EOP'
- self.ss_block = self.samplenum
- self.get_eop(sym)
- return
- self.syms.append(sym)
+ self.ss_block = self.samplenum_lastedge
+ else:
+ b = '0' if self.oldsym != sym else '1'
+ self.handle_bit(b)
self.putpb(['SYM', sym])
- b = '0' if self.oldsym != sym else '1'
self.putb(sym_annotation[sym])
if self.oldsym != sym:
edgesym = symbols[self.options['signalling']][tuple(self.edgepins)]
else:
self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
self.samplepos = self.samplepos + (0.01 * self.bitwidth)
- self.handle_bit(sym, b)
- self.set_new_target_samplenum()
self.oldsym = sym
def decode(self, ss, es, data):