uart: Remove redundant "reached bit" checks

[libsigrokdecode.git] / decoders / uart / pd.py

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 8db3e172dcc4f14ee56fff0fe1062d8188a2f275..6a0dff9dfc8f36bc7d893c5e441ea5d4e57bd880 100644 (file)
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -195,30 +195,13 @@ class Decoder(srd.Decoder):
         bitpos += bitnum * self.bit_width
         return bitpos
 
-    # Return true if we reached the middle of the desired bit, false otherwise.
-    def reached_bit(self, rxtx, bitnum):
-        bitpos = self.get_sample_point(rxtx, bitnum)
-        if self.samplenum >= bitpos:
-            return True
-        return False
-
     def wait_for_start_bit(self, rxtx, signal):
-        # The caller already has detected an edge. Strictly speaking this
-        # check on the current signal level is redundant. But it does not
-        # harm either.
-        if signal != 0:
-            return
-
         # Save the sample number where the start bit begins.
         self.frame_start[rxtx] = self.samplenum
 
         self.state[rxtx] = 'GET START BIT'
 
     def get_start_bit(self, rxtx, signal):
-        # Skip samples until we're in the middle of the start bit.
-        if not self.reached_bit(rxtx, 0):
-            return
-
         self.startbit[rxtx] = signal
 
         # The startbit must be 0. If not, we report an error and wait
@@ -239,10 +222,6 @@ class Decoder(srd.Decoder):
         self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
 
     def get_data_bits(self, rxtx, signal):
-        # Skip samples until we're in the middle of the desired data bit.
-        if not self.reached_bit(rxtx, 1 + self.cur_data_bit[rxtx]):
-            return
-
         # Save the sample number of the middle of the first data bit.
         if self.startsample[rxtx] == -1:
             self.startsample[rxtx] = self.samplenum
@@ -330,10 +309,6 @@ class Decoder(srd.Decoder):
         return None
 
     def get_parity_bit(self, rxtx, signal):
-        # Skip samples until we're in the middle of the parity bit.
-        if not self.reached_bit(rxtx, 1 + self.options['num_data_bits']):
-            return
-
         self.paritybit[rxtx] = signal
 
         self.state[rxtx] = 'GET STOP BITS'
@@ -349,12 +324,6 @@ class Decoder(srd.Decoder):
 
     # TODO: Currently only supports 1 stop bit.
     def get_stop_bits(self, rxtx, signal):
-        # Skip samples until we're in the middle of the stop bit(s).
-        skip_parity = 0 if self.options['parity_type'] == 'none' else 1
-        b = 1 + self.options['num_data_bits'] + skip_parity
-        if not self.reached_bit(rxtx, b):
-            return
-
         self.stopbit1[rxtx] = signal
 
         # Stop bits must be 1. If not, we report an error.
@@ -395,6 +364,24 @@ class Decoder(srd.Decoder):
         cond = {'skip': want_num - self.samplenum}
         return cond
 
+    def inspect_sample(self, rxtx, signal, inv):
+        """Inspect a sample returned by .wait() for the specified UART line."""
+
+        if inv:
+            signal = not signal
+
+        state = self.state[rxtx]
+        if state == 'WAIT FOR START BIT':
+            self.wait_for_start_bit(rxtx, signal)
+        elif state == 'GET START BIT':
+            self.get_start_bit(rxtx, signal)
+        elif state == 'GET DATA BITS':
+            self.get_data_bits(rxtx, signal)
+        elif state == 'GET PARITY BIT':
+            self.get_parity_bit(rxtx, signal)
+        elif state == 'GET STOP BITS':
+            self.get_stop_bits(rxtx, signal)
+
     def decode(self):
         if not self.samplerate:
             raise SamplerateError('Cannot decode without samplerate.')
@@ -405,34 +392,18 @@ class Decoder(srd.Decoder):
 
         opt = self.options
         inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes']
+        cond_idx = [None] * len(has_pin)
 
         while True:
             conds = []
             if has_pin[RX]:
+                cond_idx[RX] = len(conds)
                 conds.append(self.get_wait_cond(RX, inv[RX]))
             if has_pin[TX]:
+                cond_idx[TX] = len(conds)
                 conds.append(self.get_wait_cond(TX, inv[TX]))
             (rx, tx) = self.wait(conds)
-            if inv[RX]:
-                rx = not rx
-            if inv[TX]:
-                tx = not tx
-
-            # State machine.
-            for rxtx in (RX, TX):
-                # Don't try to handle RX (or TX) if not supplied.
-                if not has_pin[rxtx]:
-                    continue
-
-                signal = rx if (rxtx == RX) else tx
-
-                if self.state[rxtx] == 'WAIT FOR START BIT':
-                    self.wait_for_start_bit(rxtx, signal)
-                elif self.state[rxtx] == 'GET START BIT':
-                    self.get_start_bit(rxtx, signal)
-                elif self.state[rxtx] == 'GET DATA BITS':
-                    self.get_data_bits(rxtx, signal)
-                elif self.state[rxtx] == 'GET PARITY BIT':
-                    self.get_parity_bit(rxtx, signal)
-                elif self.state[rxtx] == 'GET STOP BITS':
-                    self.get_stop_bits(rxtx, signal)
+            if cond_idx[RX] is not None and self.matched[cond_idx[RX]]:
+                self.inspect_sample(RX, rx, inv[RX])
+            if cond_idx[TX] is not None and self.matched[cond_idx[TX]]:
+                self.inspect_sample(TX, tx, inv[TX])