uart: Allow either RX or TX to be optional.

[libsigrokdecode.git] / decoders / uart / pd.py

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index c3d1b62dbc5849f16fc4c5cf91f322cf8dfd36f9..18507cf7597924516342f0aceafcb2963af2c892 100644 (file)
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -18,12 +18,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# UART protocol decoder
-
 import sigrokdecode as srd
 
 '''
-Protocol output format:
+OUTPUT_PYTHON format:
 
 UART packet:
 [<packet-type>, <rxtx>, <packet-data>]
@@ -79,13 +77,13 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['uart']
-    probes = [
+    probes = []
+    optional_probes = [
         # Allow specifying only one of the signals, e.g. if only one data
         # direction exists (or is relevant).
         {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
         {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
     ]
-    optional_probes = []
     options = {
         'baudrate': ['Baud rate', 115200],
         'num_data_bits': ['Data bits', 8], # Valid: 5-9.
@@ -97,12 +95,12 @@ class Decoder(srd.Decoder):
         # TODO: Options to invert the signal(s).
     }
     annotations = [
-        ['RX data', 'UART RX data'],
-        ['TX data', 'UART TX data'],
-        ['Start bits', 'UART start bits'],
-        ['Parity bits', 'UART parity bits'],
-        ['Stop bits', 'UART stop bits'],
-        ['Warnings', 'Warnings'],
+        ['rx-data', 'UART RX data'],
+        ['tx-data', 'UART TX data'],
+        ['start-bits', 'UART start bits'],
+        ['parity-bits', 'UART parity bits'],
+        ['stop-bits', 'UART stop bits'],
+        ['warnings', 'Warnings'],
     ]
     binary = (
         ('rx', 'RX dump'),
@@ -120,7 +118,7 @@ class Decoder(srd.Decoder):
 
     def putp(self, data):
         s, halfbit = self.samplenum, int(self.bit_width / 2)
-        self.put(s - halfbit, s + halfbit, self.out_proto, data)
+        self.put(s - halfbit, s + halfbit, self.out_python, data)
 
     def putbin(self, rxtx, data):
         s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
@@ -141,7 +139,7 @@ class Decoder(srd.Decoder):
         self.oldpins = [1, 1]
 
     def start(self):
-        self.out_proto = self.register(srd.OUTPUT_PYTHON)
+        self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_bin = self.register(srd.OUTPUT_BINARY)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
@@ -232,7 +230,7 @@ class Decoder(srd.Decoder):
 
         b, f = self.databyte[rxtx], self.options['format']
         if f == 'ascii':
-            c = chr(b) if chr(b).isprintable() else '[%02X]' % b
+            c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b
             self.putx(rxtx, [rxtx, [c]])
         elif f == 'dec':
             self.putx(rxtx, [rxtx, [str(b)]])
@@ -295,7 +293,6 @@ class Decoder(srd.Decoder):
     def decode(self, ss, es, data):
         if self.samplerate is None:
             raise Exception("Cannot decode without samplerate.")
-        # TODO: Either RX or TX could be omitted (optional probe).
         for (self.samplenum, pins) in data:
 
             # Note: Ignoring identical samples here for performance reasons
@@ -304,8 +301,17 @@ class Decoder(srd.Decoder):
             #     continue
             self.oldpins, (rx, tx) = pins, pins
 
+            # Either RX or TX (but not both) can be omitted.
+            has_pin = [rx in (0, 1), tx in (0, 1)]
+            if has_pin == [False, False]:
+                raise Exception('Either TX or RX (or both) pins required.')
+
             # State machine.
             for rxtx in (RX, TX):
+                # Don't try to handle RX (or TX) if not supplied.
+                if not has_pin[rxtx]:
+                    continue
+
                 signal = rx if (rxtx == RX) else tx
 
                 if self.state[rxtx] == 'WAIT FOR START BIT':