import sigrokdecode as srd
'''
-Protocol output format:
+OUTPUT_PYTHON format:
UART packet:
[<packet-type>, <rxtx>, <packet-data>]
license = 'gplv2+'
inputs = ['logic']
outputs = ['uart']
- probes = [
+ probes = []
+ optional_probes = [
# Allow specifying only one of the signals, e.g. if only one data
# direction exists (or is relevant).
{'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
{'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
]
- optional_probes = []
options = {
'baudrate': ['Baud rate', 115200],
'num_data_bits': ['Data bits', 8], # Valid: 5-9.
def putp(self, data):
s, halfbit = self.samplenum, int(self.bit_width / 2)
- self.put(s - halfbit, s + halfbit, self.out_proto, data)
+ self.put(s - halfbit, s + halfbit, self.out_python, data)
def putbin(self, rxtx, data):
s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
self.oldpins = [1, 1]
def start(self):
- self.out_proto = self.register(srd.OUTPUT_PYTHON)
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_bin = self.register(srd.OUTPUT_BINARY)
self.out_ann = self.register(srd.OUTPUT_ANN)
def decode(self, ss, es, data):
if self.samplerate is None:
raise Exception("Cannot decode without samplerate.")
- # TODO: Either RX or TX could be omitted (optional probe).
for (self.samplenum, pins) in data:
# Note: Ignoring identical samples here for performance reasons
# continue
self.oldpins, (rx, tx) = pins, pins
+ # Either RX or TX (but not both) can be omitted.
+ has_pin = [rx in (0, 1), tx in (0, 1)]
+ if has_pin == [False, False]:
+ raise Exception('Either TX or RX (or both) pins required.')
+
# State machine.
for rxtx in (RX, TX):
+ # Don't try to handle RX (or TX) if not supplied.
+ if not has_pin[rxtx]:
+ continue
+
signal = rx if (rxtx == RX) else tx
if self.state[rxtx] == 'WAIT FOR START BIT':