## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# Parallel (sync) bus protocol decoder
-
import sigrokdecode as srd
'''
-Protocol output format:
+OUTPUT_PYTHON format:
Packet:
[<ptype>, <pdata>]
'''
def probe_list(num_probes):
- l = []
+ l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}]
for i in range(num_probes):
d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
l.append(d)
license = 'gplv2+'
inputs = ['logic']
outputs = ['parallel']
- probes = [
- {'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'},
- ]
optional_probes = probe_list(8)
- options = {
- 'clock_edge': ['Clock edge to sample on', 'rising'],
- 'wordsize': ['Word size of the data', 1],
- 'endianness': ['Endianness of the data', 'little'],
- 'format': ['Data format', 'hex'],
- }
+ options = (
+ {'id': 'clock_edge', 'desc': 'Clock edge to sample on',
+ 'default': 'rising', 'values': ('rising', 'falling')},
+ {'id': 'wordsize', 'desc': 'Word size of the data',
+ 'default': 1},
+ {'id': 'endianness', 'desc': 'Endianness of the data',
+ 'default': 'little', 'values': ('little', 'big')},
+ )
annotations = [
['items', 'Items'],
['words', 'Words'],
self.first = True
self.state = 'IDLE'
- def start(self, metadata):
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'parallel')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'parallel')
-
- def report(self):
- pass
+ def start(self):
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
def putpb(self, data):
- self.put(self.ss_item, self.es_item, self.out_proto, data)
+ self.put(self.ss_item, self.es_item, self.out_python, data)
def putb(self, data):
self.put(self.ss_item, self.es_item, self.out_ann, data)
def putpw(self, data):
- self.put(self.ss_word, self.es_word, self.out_proto, data)
+ self.put(self.ss_word, self.es_word, self.out_python, data)
def putw(self, data):
self.put(self.ss_word, self.es_word, self.out_ann, data)
if self.itemcount < ws:
return
- # Output annotations/proto for a word (a collection of items).
+ # Output annotations/python for a word (a collection of items).
word = 0
for i in range(ws):
if endian == 'little':
# State machine.
if self.state == 'IDLE':
- self.find_clk_edge(pins[0], pins[1:])
+ if pins[0] not in (0, 1):
+ self.handle_bits(pins[1:])
+ else:
+ self.find_clk_edge(pins[0], pins[1:])
else:
raise Exception('Invalid state: %s' % self.state)