parallel: unify decode() code paths with and without clock signal

[libsigrokdecode.git] / decoders / parallel / pd.py

diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py
index 140b7b8b34a6f5f3eb697977d688a9f59c8bcfa6..4c09d86235e45b0d332511f91826ae59c364e191 100644 (file)
--- a/decoders/parallel/pd.py
+++ b/decoders/parallel/pd.py
@@ -176,10 +176,11 @@ class Decoder(srd.Decoder):
             for i in range(1, len(self.optional_channels)):
                 if self.has_channel(i):
                     conds.append({i: 'e'})
-            while True:
-                self.handle_bits(self.wait(conds)[1:])
         else:
             # Sample on the rising or falling CLK edge (depends on config).
-            while True:
-                pins = self.wait({0: self.options['clock_edge'][0]})
-                self.handle_bits(pins[1:])
+            edge = self.options['clock_edge'][0]
+            conds = [{0: edge}]
+
+        while True:
+            pins = self.wait(conds)
+            self.handle_bits(pins[1:])