## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
-# LPC protocol decoder
-
import sigrokdecode as srd
# ...
}
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 3
id = 'lpc'
name = 'LPC'
- longname = 'Low-Pin-Count'
+ longname = 'Low Pin Count'
desc = 'Protocol for low-bandwidth devices on PC mainboards.'
license = 'gplv2+'
inputs = ['logic']
- outputs = ['lpc']
- probes = [
- {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'TODO'},
- {'id': 'lclk', 'name': 'LCLK', 'desc': 'TODO'},
- {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'TODO'},
- {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'TODO'},
- {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'TODO'},
- {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'TODO'},
- ]
- optional_probes = [
- {'id': 'lreset', 'name': 'LRESET#', 'desc': 'TODO'},
- {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'TODO'},
- {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'TODO'},
- {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'TODO'},
- {'id': 'lpme', 'name': 'LPME#', 'desc': 'TODO'},
- {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'TODO'},
- {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'TODO'},
- ]
- options = {}
- annotations = [
- ['warnings', 'Warnings'],
- ['start', 'Start'],
- ['cycle_type', 'Cycle-type/direction'],
- ['addr', 'Address'],
- ['tar1', 'Turn-around cycle 1'],
- ['sync', 'Sync'],
- ['data', 'Data'],
- ['tar2', 'Turn-around cycle 2'],
- ]
-
- def __init__(self, **kwargs):
+ outputs = []
+ tags = ['PC']
+ channels = (
+ {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'},
+ {'id': 'lclk', 'name': 'LCLK', 'desc': 'Clock'},
+ {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'Addr/control/data 0'},
+ {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'Addr/control/data 1'},
+ {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'Addr/control/data 2'},
+ {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'Addr/control/data 3'},
+ )
+ optional_channels = (
+ {'id': 'lreset', 'name': 'LRESET#', 'desc': 'Reset'},
+ {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'Encoded DMA / bus master request'},
+ {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'Serialized IRQ'},
+ {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'Clock run'},
+ {'id': 'lpme', 'name': 'LPME#', 'desc': 'LPC power management event'},
+ {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'Power down'},
+ {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'System Management Interrupt'},
+ )
+ annotations = (
+ ('warning', 'Warning'),
+ ('start', 'Start'),
+ ('cycle-type', 'Cycle-type/direction'),
+ ('addr', 'Address'),
+ ('tar1', 'Turn-around cycle 1'),
+ ('sync', 'Sync'),
+ ('data', 'Data'),
+ ('tar2', 'Turn-around cycle 2'),
+ )
+ annotation_rows = (
+ ('data-vals', 'Data', (1, 2, 3, 4, 5, 6, 7)),
+ ('warnings', 'Warnings', (0,)),
+ )
+
+ def __init__(self):
+ self.reset()
+
+ def reset(self):
self.state = 'IDLE'
self.oldlclk = -1
- self.samplenum = 0
- self.clocknum = 0
self.lad = -1
self.addr = 0
self.cur_nibble = 0
self.ss_block = self.es_block = None
def start(self):
- # self.out_proto = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
def putb(self, data):
def handle_get_ct_dr(self, lad, lad_bits):
# LAD[3:0]: Cycle type / direction field (1 clock cycle).
- self.cycle_type = fields['CT_DR'][lad]
+ self.cycle_type = fields['CT_DR'].get(lad, 'Reserved / unknown')
# TODO: Warning/error on invalid cycle types.
- if self.cycle_type == 'Reserved':
+ if 'Reserved' in self.cycle_type:
self.putb([0, ['Invalid cycle type (%s)' % lad_bits]])
self.es_block = self.samplenum
# LAD[3:0]: SYNC field (1-n clock cycles).
self.sync_val = lad_bits
- self.cycle_type = fields['SYNC'][lad]
+ self.cycle_type = fields['SYNC'].get(lad, 'Reserved / unknown')
# TODO: Warnings if reserved value are seen?
- if self.cycle_type == 'Reserved':
+ if 'Reserved' in self.cycle_type:
self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \
(self.synccount, self.sync_val)]])
self.tarcount = 0
self.state = 'IDLE'
- def decode(self, ss, es, data):
- for (self.samplenum, pins) in data:
-
- # If none of the pins changed, there's nothing to do.
- if self.oldpins == pins:
- continue
+ def decode(self):
+ conditions = [{i: 'e'} for i in range(6)]
+ while True:
+ pins = self.wait(conditions)
# Store current pin values for the next round.
self.oldpins = pins
# Most (but not all) states need this.
if self.state != 'IDLE':
lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0
- lad_bits = bin(lad)[2:].zfill(4)
+ lad_bits = '{:04b}'.format(lad)
# self.putb([0, ['LAD: %s' % lad_bits]])
# TODO: Only memory read/write is currently supported/tested.
if self.state == 'IDLE':
# A valid LPC cycle starts with LFRAME# being asserted (low).
if lframe != 0:
- continue
+ continue
self.ss_block = self.samplenum
self.state = 'GET START'
self.lad = -1
- # self.clocknum = 0
elif self.state == 'GET START':
self.handle_get_start(lad, lad_bits, lframe)
elif self.state == 'GET CT/DR':
self.handle_get_data(lad, lad_bits)
elif self.state == 'GET TAR2':
self.handle_get_tar2(lad, lad_bits)
- else:
- raise Exception('Invalid state: %s' % self.state)
-
projects / libsigrokdecode.git / blobdiff