avr_isp: Add more parts

[libsigrokdecode.git] / decoders / lpc / pd.py

diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py
index cdd1db8f4e6d25f696887adbe0893794453809b8..2a88e30473841140682d14fb513a3044158661bf 100644 (file)
--- a/decoders/lpc/pd.py
+++ b/decoders/lpc/pd.py
@@ -98,11 +98,12 @@ class Decoder(srd.Decoder):
     api_version = 3
     id = 'lpc'
     name = 'LPC'
-    longname = 'Low-Pin-Count'
+    longname = 'Low Pin Count'
     desc = 'Protocol for low-bandwidth devices on PC mainboards.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['lpc']
+    outputs = []
+    tags = ['PC']
     channels = (
         {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'},
         {'id': 'lclk',   'name': 'LCLK',    'desc': 'Clock'},
@@ -121,7 +122,7 @@ class Decoder(srd.Decoder):
         {'id': 'lsmi',   'name': 'LSMI#',   'desc': 'System Management Interrupt'},
     )
     annotations = (
-        ('warnings', 'Warnings'),
+        ('warning', 'Warning'),
         ('start', 'Start'),
         ('cycle-type', 'Cycle-type/direction'),
         ('addr', 'Address'),
@@ -131,15 +132,16 @@ class Decoder(srd.Decoder):
         ('tar2', 'Turn-around cycle 2'),
     )
     annotation_rows = (
-        ('data', 'Data', (1, 2, 3, 4, 5, 6, 7)),
+        ('data-vals', 'Data', (1, 2, 3, 4, 5, 6, 7)),
         ('warnings', 'Warnings', (0,)),
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.state = 'IDLE'
         self.oldlclk = -1
-        self.samplenum = 0
-        self.clocknum = 0
         self.lad = -1
         self.addr = 0
         self.cur_nibble = 0
@@ -183,10 +185,10 @@ class Decoder(srd.Decoder):
     def handle_get_ct_dr(self, lad, lad_bits):
         # LAD[3:0]: Cycle type / direction field (1 clock cycle).
 
-        self.cycle_type = fields['CT_DR'][lad]
+        self.cycle_type = fields['CT_DR'].get(lad, 'Reserved / unknown')
 
         # TODO: Warning/error on invalid cycle types.
-        if self.cycle_type == 'Reserved':
+        if 'Reserved' in self.cycle_type:
             self.putb([0, ['Invalid cycle type (%s)' % lad_bits]])
 
         self.es_block = self.samplenum
@@ -252,10 +254,10 @@ class Decoder(srd.Decoder):
         # LAD[3:0]: SYNC field (1-n clock cycles).
 
         self.sync_val = lad_bits
-        self.cycle_type = fields['SYNC'][lad]
+        self.cycle_type = fields['SYNC'].get(lad, 'Reserved / unknown')
 
         # TODO: Warnings if reserved value are seen?
-        if self.cycle_type == 'Reserved':
+        if 'Reserved' in self.cycle_type:
             self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \
                            (self.synccount, self.sync_val)]])
 
@@ -313,13 +315,9 @@ class Decoder(srd.Decoder):
         self.state = 'IDLE'
 
     def decode(self):
+        conditions = [{i: 'e'} for i in range(6)]
         while True:
-            # TODO: Come up with more appropriate self.wait() conditions.
-            pins = self.wait()
-
-            # If none of the pins changed, there's nothing to do.
-            if self.oldpins == pins:
-                continue
+            pins = self.wait(conditions)
 
             # Store current pin values for the next round.
             self.oldpins = pins
@@ -338,7 +336,7 @@ class Decoder(srd.Decoder):
             # Most (but not all) states need this.
             if self.state != 'IDLE':
                 lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0
-                lad_bits = bin(lad)[2:].zfill(4)
+                lad_bits = '{:04b}'.format(lad)
                 # self.putb([0, ['LAD: %s' % lad_bits]])
 
             # TODO: Only memory read/write is currently supported/tested.
@@ -351,7 +349,6 @@ class Decoder(srd.Decoder):
                 self.ss_block = self.samplenum
                 self.state = 'GET START'
                 self.lad = -1
-                # self.clocknum = 0
             elif self.state == 'GET START':
                 self.handle_get_start(lad, lad_bits, lframe)
             elif self.state == 'GET CT/DR':