##
## This file is part of the libsigrokdecode project.
##
-## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# ST STM32 JTAG protocol decoder
-
import sigrokdecode as srd
# JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
0xfc: ['IDR', 'Identification register'],
}
-# TODO: All start/end sample values in self.put() calls are bogus.
# TODO: Split off generic ARM/Cortex-M3 parts into another protocol decoder?
# Bits[31:28]: Version (here: 0x3)
% (data_hex, ack_meaning)
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 2
id = 'jtag_stm32'
name = 'JTAG / STM32'
longname = 'Joint Test Action Group / ST STM32'
license = 'gplv2+'
inputs = ['jtag']
outputs = ['jtag_stm32']
- probes = []
- optional_probes = []
- options = {}
- annotations = [
- ['Text', 'Human-readable text'],
- ]
+ annotations = (
+ ('item', 'Item'),
+ ('field', 'Field'),
+ ('command', 'Command'),
+ ('warning', 'Warning'),
+ )
+ annotation_rows = (
+ ('items', 'Items', (0,)),
+ ('fields', 'Fields', (1,)),
+ ('commands', 'Commands', (2,)),
+ ('warnings', 'Warnings', (3,)),
+ )
def __init__(self, **kwargs):
self.state = 'IDLE'
- # self.state = 'BYPASS'
+ self.samplenums = None
def start(self):
- # self.out_proto = self.add(srd.OUTPUT_PYTHON, 'jtag_stm32')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag_stm32')
+ self.out_ann = self.register(srd.OUTPUT_ANN)
+
+ def putx(self, data):
+ self.put(self.ss, self.es, self.out_ann, data)
- def report(self):
- pass
+ def putf(self, s, e, data):
+ self.put(self.samplenums[s][0], self.samplenums[e][1], self.out_ann, data)
def handle_reg_bypass(self, cmd, bits):
- # TODO
- self.put(self.ss, self.es, self.out_ann, [0, ['BYPASS: ' + bits]])
+ self.putx([0, ['BYPASS: ' + bits]])
def handle_reg_idcode(self, cmd, bits):
- # TODO
# IDCODE is a read-only register which is always accessible.
# IR == IDCODE: The device ID code is shifted out via DR next.
- self.put(self.ss, self.es, self.out_ann,
- [0, ['IDCODE: %s (ver=%s, part=%s, manuf=%s, res=%s)' % \
- decode_device_id_code(bits)]])
+
+ s = self.samplenums
+ s.reverse()
+ id_hex, ver, part, manuf, res = decode_device_id_code(bits[:-1])
+ self.putf(0, 0, [1, ['Reserved (BS TAP)', 'BS', 'B']])
+ self.putf(1, 1, [1, ['Reserved', 'Res', 'R']])
+ self.putf(2, 12, [1, ['Manufacturer: %s' % manuf, 'Manuf', 'M']])
+ self.putf(13, 28, [1, ['Part: %s' % part, 'Part', 'P']])
+ self.putf(29, 32, [1, ['Version: %s' % ver, 'Version', 'V']])
+
+ self.ss = s[1][0]
+ self.putx([2, ['IDCODE: %s (ver=%s, part=%s, manuf=%s, res=%s)' % \
+ decode_device_id_code(bits[:-1])]])
def handle_reg_dpacc(self, cmd, bits):
- # self.put(self.ss, self.es, self.out_ann,
- # [0, ['DPACC/%s: %s' % (cmd, bits)]])
+ bits = bits[:-1]
s = data_in('DPACC', bits) if (cmd == 'DR TDI') else data_out(bits)
- self.put(self.ss, self.es, self.out_ann, [0, [s]])
+ self.putx([2, [s]])
def handle_reg_apacc(self, cmd, bits):
- # self.put(self.ss, self.es, self.out_ann,
- # [0, ['APACC/%s: %s' % (cmd, bits)]])
+ bits = bits[:-1]
s = data_in('APACC', bits) if (cmd == 'DR TDI') else data_out(bits)
- self.put(self.ss, self.es, self.out_ann, [0, [s]])
+ self.putx([2, [s]])
def handle_reg_abort(self, cmd, bits):
+ bits = bits[:-1]
# Bits[31:1]: reserved. Bit[0]: DAPABORT.
a = '' if (bits[0] == '1') else 'No '
s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
- self.put(self.ss, self.es, self.out_ann, [0, [s]])
+ self.putx([2, [s]])
# Warn if DAPABORT[31:1] contains non-zero bits.
if (bits[:-1] != ('0' * 31)):
- self.put(self.ss, self.es, self.out_ann,
- [0, ['WARNING: DAPABORT[31:1] reserved!']])
+ self.putx([3, ['WARNING: DAPABORT[31:1] reserved!']])
def handle_reg_unknown(self, cmd, bits):
- self.put(self.ss, self.es, self.out_ann,
- [0, ['Unknown instruction: ' % bits]]) # TODO
+ bits = bits[:-1]
+ self.putx([2, ['Unknown instruction: %s' % bits]])
def decode(self, ss, es, data):
- # Assumption: The right-most char in the 'val' bitstring is the LSB.
cmd, val = data
self.ss, self.es = ss, es
- # self.put(self.ss, self.es, self.out_ann, [0, [cmd + ' / ' + val]])
+ if cmd != 'NEW STATE':
+ # The right-most char in the 'val' bitstring is the LSB.
+ val, self.samplenums = val
# State machine
if self.state == 'IDLE':
if cmd != 'IR TDI':
return
# Switch to the state named after the instruction, or 'UNKNOWN'.
- # Ignore bits other than IR[3:0]. While the IR register is only
- # 4 bits in size, some programs (e.g. OpenOCD) might fill in a
- # few more (dummy) bits. OpenOCD makes IR at least 8 bits long.
- self.state = ir.get(val[-4:], ['UNKNOWN', 0])[0]
- self.put(self.ss, self.es, self.out_ann, [0, ['IR: ' + self.state]])
+ # The STM32F10xxx has two serially connected JTAG TAPs, the
+ # boundary scan tap (5 bits) and the Cortex-M3 TAP (4 bits).
+ # See UM 31.5 "STM32F10xxx JTAG TAP connection" for details.
+ self.state = ir.get(val[:-1][-4:], ['UNKNOWN', 0])[0]
+ bstap_ir = ir.get(val[:-1][:4], ['UNKNOWN', 0])[0]
+ self.putf(3, 0, [1, ['IR (BS TAP): ' + bstap_ir]])
+ self.putf(7, 4, [1, ['IR (M3 TAP): ' + self.state]])
+ self.putf(8, 8, [1, ['Reserved (BS TAP)', 'BS', 'B']])
+ self.putx([2, ['IR: %s' % self.state]])
elif self.state == 'BYPASS':
# Here we're interested in incoming bits (TDI).
if cmd != 'DR TDI':
return
handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
handle_reg(cmd, val)
- if cmd == 'DR TDO': # TODO: Assumes 'DR TDI' comes before 'DR TDO'
+ if cmd == 'DR TDO': # Assumes 'DR TDI' comes before 'DR TDO'.
self.state = 'IDLE'
- else:
- raise Exception('Invalid state: %s' % self.state)
-
projects / libsigrokdecode.git / blobdiff