avr_isp: Add more parts

[libsigrokdecode.git] / decoders / ad79x0 / pd.py

diff --git a/decoders/ad79x0/pd.py b/decoders/ad79x0/pd.py
index 13a29723e7f0ffda362f62a521067a0e504e7ae6..3d7ab7315b5479ed06d87288b383a4630a5e50ed 100644 (file)
--- a/decoders/ad79x0/pd.py
+++ b/decoders/ad79x0/pd.py
@@ -25,7 +25,7 @@ modes = {
     2: ['Power Up Mode', 'Power Up', 'PU'],
 }
 
-input_voltage_format = ['%fV', '%fV', '%.6fV', '%.2fV']
+input_voltage_format = ['%.6fV', '%.2fV']
 
 validation = {
     'invalid': ['Invalid data', 'Invalid', 'N/A'],
@@ -42,7 +42,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['spi']
     outputs = []
-    tags = ['Display']
+    tags = ['IC', 'Analog/digital']
     annotations = (
         ('mode', 'Mode'),
         ('voltage', 'Voltage'),
@@ -54,7 +54,7 @@ class Decoder(srd.Decoder):
         ('data_validation', 'Data validation', (2,)),
     )
     options = (
-        {'id': 'ref', 'desc': 'Reference voltage', 'default': 1.5},
+        {'id': 'vref', 'desc': 'Reference voltage (V)', 'default': 1.5},
     )
 
     def __init__(self,):
@@ -108,7 +108,7 @@ class Decoder(srd.Decoder):
                             self.put_validation([self.start_sample, es], 'complete')
                         elif nb_bits < 16:
                             self.put_validation([self.start_sample, es], 'incomplete')
-                        vin = (self.data / ((2**12) - 1)) * self.options['ref']
+                        vin = (self.data / ((2**12) - 1)) * self.options['vref']
                         self.put_data([self.start_sample, es], vin)
                 elif nb_bits < 10:
                     self.put_mode([self.start_sample, es], 1)