[libsigrokdecode.git] / decoders / jtag_stm32 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

# JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
# Note: The ARM DAP-DP is not IEEE 1149.1 (JTAG) compliant (as per ARM docs),
#       as it does not implement the EXTEST, SAMPLE, and PRELOAD instructions.
#       Instead, BYPASS is decoded for any of these instructions.
ir = {
    '1111': ['BYPASS', 1],  # Bypass register
    '1110': ['IDCODE', 32], # ID code register
    '1010': ['DPACC', 35],  # Debug port access register
    '1011': ['APACC', 35],  # Access port access register
    '1000': ['ABORT', 35],  # Abort register # TODO: 32 bits? Datasheet typo?
}

# ARM Cortex-M3 r1p1-01rel0 ID code
cm3_idcode = 0x3ba00477

# http://infocenter.arm.com/help/topic/com.arm.doc.ddi0413c/Chdjibcg.html
cm3_idcode_ver = {
    0x3: 'JTAG-DP',
    0x2: 'SW-DP',
}
cm3_idcode_part = {
    0xba00: 'JTAG-DP',
    0xba10: 'SW-DP',
}

# http://infocenter.arm.com/help/topic/com.arm.doc.faqs/ka14408.html
jedec_id = {
    5: {
        0x3b: 'ARM Ltd.',
    },
}

# JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP
jtag_idcode = {
    0x06412041: 'Low-density device, rev. A',
    0x06410041: 'Medium-density device, rev. A',
    0x16410041: 'Medium-density device, rev. B/Z/Y',
    0x06414041: 'High-density device, rev. A/Z/Y',
    0x06430041: 'XL-density device, rev. A',
    0x06418041: 'Connectivity-line device, rev. A/Z',
}

# ACK[2:0] in the DPACC/APACC registers (unlisted values are reserved)
ack_val = {
    '001': 'WAIT',
    '010': 'OK/FAULT',
}

# 32bit debug port registers (addressed via A[3:2])
dp_reg = {
    '00': 'Reserved', # Must be kept at reset value
    '01': 'DP CTRL/STAT',
    '10': 'DP SELECT',
    '11': 'DP RDBUFF',
}

# APB-AP registers (each of them 32 bits wide)
apb_ap_reg = {
    0x00: ['CSW', 'Control/status word'],
    0x04: ['TAR', 'Transfer address'],
    # 0x08: Reserved SBZ
    0x0c: ['DRW', 'Data read/write'],
    0x10: ['BD0', 'Banked data 0'],
    0x14: ['BD1', 'Banked data 1'],
    0x18: ['BD2', 'Banked data 2'],
    0x1c: ['BD3', 'Banked data 3'],
    # 0x20-0xf4: Reserved SBZ
    0x800000000: ['ROM', 'Debug ROM address'],
    0xfc: ['IDR', 'Identification register'],
}

# TODO: Split off generic ARM/Cortex-M3 parts into another protocol decoder?

# Bits[31:28]: Version (here: 0x3)
#              JTAG-DP: 0x3, SW-DP: 0x2
# Bits[27:12]: Part number (here: 0xba00)
#              JTAG-DP: 0xba00, SW-DP: 0xba10
# Bits[11:1]:  JEDEC (JEP-106) manufacturer ID (here: 0x23b)
#              Bits[11:8]: Continuation code ('ARM Ltd.': 0x04)
#              Bits[7:1]: Identity code ('ARM Ltd.': 0x3b)
# Bits[0:0]:   Reserved (here: 0x1)
def decode_device_id_code(bits):
    id_hex = '0x%x' % int('0b' + bits, 2)
    ver = cm3_idcode_ver.get(int('0b' + bits[-32:-28], 2), 'UNKNOWN')
    part = cm3_idcode_part.get(int('0b' + bits[-28:-12], 2), 'UNKNOWN')
    ids = jedec_id.get(int('0b' + bits[-12:-8], 2) + 1, {})
    manuf = ids.get(int('0b' + bits[-7:-1], 2), 'UNKNOWN')
    return (id_hex, manuf, ver, part)

# DPACC is used to access debug port registers (CTRL/STAT, SELECT, RDBUFF).
# APACC is used to access all Access Port (AHB-AP) registers.

# APACC/DPACC, when transferring data IN:
# Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
# Bits[2:1] = A[3:2]: 2-bit address (debug/access port register)
# Bits[0:0] = RnW: Read request (1) or write request (0)
def data_in(instruction, bits):
    data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
    data_hex = '0x%x' % int('0b' + data, 2)
    r = 'Read request' if (rnw == '1') else 'Write request'
    # reg = dp_reg[a] if (instruction == 'DPACC') else apb_ap_reg[a]
    reg = dp_reg[a] if (instruction == 'DPACC') else a # TODO
    return 'New transaction: DATA: %s, A: %s, RnW: %s' % (data_hex, reg, r)

# APACC/DPACC, when transferring data OUT:
# Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
# Bits[2:0] = ACK[2:0]: 3-bit acknowledge
def data_out(bits):
    data, ack = bits[:-3], bits[-3:]
    data_hex = '0x%x' % int('0b' + data, 2)
    ack_meaning = ack_val.get(ack, 'Reserved')
    return 'Previous transaction result: DATA: %s, ACK: %s' \
           % (data_hex, ack_meaning)

class Decoder(srd.Decoder):
    api_version = 2
    id = 'jtag_stm32'
    name = 'JTAG / STM32'
    longname = 'Joint Test Action Group / ST STM32'
    desc = 'ST STM32-specific JTAG protocol.'
    license = 'gplv2+'
    inputs = ['jtag']
    outputs = ['jtag_stm32']
    annotations = (
        ('item', 'Item'),
        ('field', 'Field'),
        ('command', 'Command'),
        ('warning', 'Warning'),
    )
    annotation_rows = (
        ('items', 'Items', (0,)),
        ('fields', 'Fields', (1,)),
        ('commands', 'Commands', (2,)),
        ('warnings', 'Warnings', (3,)),
    )

    def __init__(self, **kwargs):
        self.state = 'IDLE'
        self.samplenums = None

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss, self.es, self.out_ann, data)

    def putf(self, s, e, data):
        self.put(self.samplenums[s][0], self.samplenums[e][1], self.out_ann, data)

    def handle_reg_bypass(self, cmd, bits):
        self.putx([0, ['BYPASS: ' + bits]])

    def handle_reg_idcode(self, cmd, bits):
        # IDCODE is a read-only register which is always accessible.
        # IR == IDCODE: The 32bit device ID code is shifted out via DR next.

        id_hex, manuf, ver, part = decode_device_id_code(bits[:-1])
        cc = '0x%x' % int('0b' + bits[:-1][-12:-8], 2)
        ic = '0x%x' % int('0b' + bits[:-1][-7:-1], 2)

        self.putf(0, 0, [1, ['Reserved (BS TAP)', 'BS', 'B']])
        self.putf(1, 1, [1, ['Reserved', 'Res', 'R']])
        self.putf(9, 12, [0, ['Continuation code: %s' % cc, 'CC', 'C']])
        self.putf(2, 8, [0, ['Identity code: %s' % ic, 'IC', 'I']])
        self.putf(2, 12, [1, ['Manufacturer: %s' % manuf, 'Manuf', 'M']])
        self.putf(13, 28, [1, ['Part: %s' % part, 'Part', 'P']])
        self.putf(29, 32, [1, ['Version: %s' % ver, 'Version', 'V']])

        self.ss = self.samplenums[1][0]
        self.putx([2, ['IDCODE: %s (%s: %s/%s)' % \
                  decode_device_id_code(bits[:-1])]])

    def handle_reg_dpacc(self, cmd, bits):
        bits = bits[:-1]
        s = data_in('DPACC', bits) if (cmd == 'DR TDI') else data_out(bits)
        self.putx([2, [s]])

    def handle_reg_apacc(self, cmd, bits):
        bits = bits[:-1]
        s = data_in('APACC', bits) if (cmd == 'DR TDI') else data_out(bits)
        self.putx([2, [s]])

    def handle_reg_abort(self, cmd, bits):
        bits = bits[:-1]
        # Bits[31:1]: reserved. Bit[0]: DAPABORT.
        a = '' if (bits[0] == '1') else 'No '
        s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
        self.putx([2, [s]])

        # Warn if DAPABORT[31:1] contains non-zero bits.
        if (bits[:-1] != ('0' * 31)):
            self.putx([3, ['WARNING: DAPABORT[31:1] reserved!']])

    def handle_reg_unknown(self, cmd, bits):
        bits = bits[:-1]
        self.putx([2, ['Unknown instruction: %s' % bits]])

    def decode(self, ss, es, data):
        cmd, val = data

        self.ss, self.es = ss, es

        if cmd != 'NEW STATE':
            # The right-most char in the 'val' bitstring is the LSB.
            val, self.samplenums = val
            self.samplenums.reverse()

        # State machine
        if self.state == 'IDLE':
            # Wait until a new instruction is shifted into the IR register.
            if cmd != 'IR TDI':
                return
            # Switch to the state named after the instruction, or 'UNKNOWN'.
            # The STM32F10xxx has two serially connected JTAG TAPs, the
            # boundary scan tap (5 bits) and the Cortex-M3 TAP (4 bits).
            # See UM 31.5 "STM32F10xxx JTAG TAP connection" for details.
            self.state = ir.get(val[:-1][-4:], ['UNKNOWN', 0])[0]
            bstap_ir = ir.get(val[:-1][:4], ['UNKNOWN', 0])[0]
            self.putf(5, 8, [1, ['IR (BS TAP): ' + bstap_ir]])
            self.putf(1, 4, [1, ['IR (M3 TAP): ' + self.state]])
            self.putf(0, 0, [1, ['Reserved (BS TAP)', 'BS', 'B']])
            self.putx([2, ['IR: %s' % self.state]])
        elif self.state == 'BYPASS':
            # Here we're interested in incoming bits (TDI).
            if cmd != 'DR TDI':
                return
            handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
            handle_reg(cmd, val)
            self.state = 'IDLE'
        elif self.state in ('IDCODE', 'ABORT', 'UNKNOWN'):
            # Here we're interested in outgoing bits (TDO).
            if cmd != 'DR TDO':
                return
            handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
            handle_reg(cmd, val)
            self.state = 'IDLE'
        elif self.state in ('DPACC', 'APACC'):
            # Here we're interested in incoming and outgoing bits (TDI/TDO).
            if cmd not in ('DR TDI', 'DR TDO'):
                return
            handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
            handle_reg(cmd, val)
            if cmd == 'DR TDO': # Assumes 'DR TDI' comes before 'DR TDO'.
                self.state = 'IDLE'
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	import sigrokdecode as srd
	22
	23	# JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
	24	# Note: The ARM DAP-DP is not IEEE 1149.1 (JTAG) compliant (as per ARM docs),
	25	# as it does not implement the EXTEST, SAMPLE, and PRELOAD instructions.
	26	# Instead, BYPASS is decoded for any of these instructions.
	27	ir = {
	28	'1111': ['BYPASS', 1], # Bypass register
	29	'1110': ['IDCODE', 32], # ID code register
	30	'1010': ['DPACC', 35], # Debug port access register
	31	'1011': ['APACC', 35], # Access port access register
	32	'1000': ['ABORT', 35], # Abort register # TODO: 32 bits? Datasheet typo?
	33	}
	34
	35	# ARM Cortex-M3 r1p1-01rel0 ID code
	36	cm3_idcode = 0x3ba00477
	37
	38	# http://infocenter.arm.com/help/topic/com.arm.doc.ddi0413c/Chdjibcg.html
	39	cm3_idcode_ver = {
	40	0x3: 'JTAG-DP',
	41	0x2: 'SW-DP',
	42	}
	43	cm3_idcode_part = {
	44	0xba00: 'JTAG-DP',
	45	0xba10: 'SW-DP',
	46	}
	47
	48	# http://infocenter.arm.com/help/topic/com.arm.doc.faqs/ka14408.html
	49	jedec_id = {
	50	5: {
	51	0x3b: 'ARM Ltd.',
	52	},
	53	}
	54
	55	# JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP
	56	jtag_idcode = {
	57	0x06412041: 'Low-density device, rev. A',
	58	0x06410041: 'Medium-density device, rev. A',
	59	0x16410041: 'Medium-density device, rev. B/Z/Y',
	60	0x06414041: 'High-density device, rev. A/Z/Y',
	61	0x06430041: 'XL-density device, rev. A',
	62	0x06418041: 'Connectivity-line device, rev. A/Z',
	63	}
	64
	65	# ACK[2:0] in the DPACC/APACC registers (unlisted values are reserved)
	66	ack_val = {
	67	'001': 'WAIT',
	68	'010': 'OK/FAULT',
	69	}
	70
	71	# 32bit debug port registers (addressed via A[3:2])
	72	dp_reg = {
	73	'00': 'Reserved', # Must be kept at reset value
	74	'01': 'DP CTRL/STAT',
	75	'10': 'DP SELECT',
	76	'11': 'DP RDBUFF',
	77	}
	78
	79	# APB-AP registers (each of them 32 bits wide)
	80	apb_ap_reg = {
	81	0x00: ['CSW', 'Control/status word'],
	82	0x04: ['TAR', 'Transfer address'],
	83	# 0x08: Reserved SBZ
	84	0x0c: ['DRW', 'Data read/write'],
	85	0x10: ['BD0', 'Banked data 0'],
	86	0x14: ['BD1', 'Banked data 1'],
	87	0x18: ['BD2', 'Banked data 2'],
	88	0x1c: ['BD3', 'Banked data 3'],
	89	# 0x20-0xf4: Reserved SBZ
	90	0x800000000: ['ROM', 'Debug ROM address'],
	91	0xfc: ['IDR', 'Identification register'],
	92	}
	93
	94	# TODO: Split off generic ARM/Cortex-M3 parts into another protocol decoder?
	95
	96	# Bits[31:28]: Version (here: 0x3)
	97	# JTAG-DP: 0x3, SW-DP: 0x2
	98	# Bits[27:12]: Part number (here: 0xba00)
	99	# JTAG-DP: 0xba00, SW-DP: 0xba10
	100	# Bits[11:1]: JEDEC (JEP-106) manufacturer ID (here: 0x23b)
	101	# Bits[11:8]: Continuation code ('ARM Ltd.': 0x04)
	102	# Bits[7:1]: Identity code ('ARM Ltd.': 0x3b)
	103	# Bits[0:0]: Reserved (here: 0x1)
	104	def decode_device_id_code(bits):
	105	id_hex = '0x%x' % int('0b' + bits, 2)
	106	ver = cm3_idcode_ver.get(int('0b' + bits[-32:-28], 2), 'UNKNOWN')
	107	part = cm3_idcode_part.get(int('0b' + bits[-28:-12], 2), 'UNKNOWN')
	108	ids = jedec_id.get(int('0b' + bits[-12:-8], 2) + 1, {})
	109	manuf = ids.get(int('0b' + bits[-7:-1], 2), 'UNKNOWN')
	110	return (id_hex, manuf, ver, part)
	111
	112	# DPACC is used to access debug port registers (CTRL/STAT, SELECT, RDBUFF).
	113	# APACC is used to access all Access Port (AHB-AP) registers.
	114
	115	# APACC/DPACC, when transferring data IN:
	116	# Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
	117	# Bits[2:1] = A[3:2]: 2-bit address (debug/access port register)
	118	# Bits[0:0] = RnW: Read request (1) or write request (0)
	119	def data_in(instruction, bits):
	120	data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
	121	data_hex = '0x%x' % int('0b' + data, 2)
	122	r = 'Read request' if (rnw == '1') else 'Write request'
	123	# reg = dp_reg[a] if (instruction == 'DPACC') else apb_ap_reg[a]
	124	reg = dp_reg[a] if (instruction == 'DPACC') else a # TODO
	125	return 'New transaction: DATA: %s, A: %s, RnW: %s' % (data_hex, reg, r)
	126
	127	# APACC/DPACC, when transferring data OUT:
	128	# Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
	129	# Bits[2:0] = ACK[2:0]: 3-bit acknowledge
	130	def data_out(bits):
	131	data, ack = bits[:-3], bits[-3:]
	132	data_hex = '0x%x' % int('0b' + data, 2)
	133	ack_meaning = ack_val.get(ack, 'Reserved')
	134	return 'Previous transaction result: DATA: %s, ACK: %s' \
	135	% (data_hex, ack_meaning)
	136
	137	class Decoder(srd.Decoder):
	138	api_version = 2
	139	id = 'jtag_stm32'
	140	name = 'JTAG / STM32'
	141	longname = 'Joint Test Action Group / ST STM32'
	142	desc = 'ST STM32-specific JTAG protocol.'
	143	license = 'gplv2+'
	144	inputs = ['jtag']
	145	outputs = ['jtag_stm32']
	146	annotations = (
	147	('item', 'Item'),
	148	('field', 'Field'),
	149	('command', 'Command'),
	150	('warning', 'Warning'),
	151	)
	152	annotation_rows = (
	153	('items', 'Items', (0,)),
	154	('fields', 'Fields', (1,)),
	155	('commands', 'Commands', (2,)),
	156	('warnings', 'Warnings', (3,)),
	157	)
	158
	159	def __init__(self, **kwargs):
	160	self.state = 'IDLE'
	161	self.samplenums = None
	162
	163	def start(self):
	164	self.out_ann = self.register(srd.OUTPUT_ANN)
	165
	166	def putx(self, data):
	167	self.put(self.ss, self.es, self.out_ann, data)
	168
	169	def putf(self, s, e, data):
	170	self.put(self.samplenums[s][0], self.samplenums[e][1], self.out_ann, data)
	171
	172	def handle_reg_bypass(self, cmd, bits):
	173	self.putx([0, ['BYPASS: ' + bits]])
	174
	175	def handle_reg_idcode(self, cmd, bits):
	176	# IDCODE is a read-only register which is always accessible.
	177	# IR == IDCODE: The 32bit device ID code is shifted out via DR next.
	178
	179	id_hex, manuf, ver, part = decode_device_id_code(bits[:-1])
	180	cc = '0x%x' % int('0b' + bits[:-1][-12:-8], 2)
	181	ic = '0x%x' % int('0b' + bits[:-1][-7:-1], 2)
	182
	183	self.putf(0, 0, [1, ['Reserved (BS TAP)', 'BS', 'B']])
	184	self.putf(1, 1, [1, ['Reserved', 'Res', 'R']])
	185	self.putf(9, 12, [0, ['Continuation code: %s' % cc, 'CC', 'C']])
	186	self.putf(2, 8, [0, ['Identity code: %s' % ic, 'IC', 'I']])
	187	self.putf(2, 12, [1, ['Manufacturer: %s' % manuf, 'Manuf', 'M']])
	188	self.putf(13, 28, [1, ['Part: %s' % part, 'Part', 'P']])
	189	self.putf(29, 32, [1, ['Version: %s' % ver, 'Version', 'V']])
	190
	191	self.ss = self.samplenums[1][0]
	192	self.putx([2, ['IDCODE: %s (%s: %s/%s)' % \
	193	decode_device_id_code(bits[:-1])]])
	194
	195	def handle_reg_dpacc(self, cmd, bits):
	196	bits = bits[:-1]
	197	s = data_in('DPACC', bits) if (cmd == 'DR TDI') else data_out(bits)
	198	self.putx([2, [s]])
	199
	200	def handle_reg_apacc(self, cmd, bits):
	201	bits = bits[:-1]
	202	s = data_in('APACC', bits) if (cmd == 'DR TDI') else data_out(bits)
	203	self.putx([2, [s]])
	204
	205	def handle_reg_abort(self, cmd, bits):
	206	bits = bits[:-1]
	207	# Bits[31:1]: reserved. Bit[0]: DAPABORT.
	208	a = '' if (bits[0] == '1') else 'No '
	209	s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
	210	self.putx([2, [s]])
	211
	212	# Warn if DAPABORT[31:1] contains non-zero bits.
	213	if (bits[:-1] != ('0' * 31)):
	214	self.putx([3, ['WARNING: DAPABORT[31:1] reserved!']])
	215
	216	def handle_reg_unknown(self, cmd, bits):
	217	bits = bits[:-1]
	218	self.putx([2, ['Unknown instruction: %s' % bits]])
	219
	220	def decode(self, ss, es, data):
	221	cmd, val = data
	222
	223	self.ss, self.es = ss, es
	224
	225	if cmd != 'NEW STATE':
	226	# The right-most char in the 'val' bitstring is the LSB.
	227	val, self.samplenums = val
	228	self.samplenums.reverse()
	229
	230	# State machine
	231	if self.state == 'IDLE':
	232	# Wait until a new instruction is shifted into the IR register.
	233	if cmd != 'IR TDI':
	234	return
	235	# Switch to the state named after the instruction, or 'UNKNOWN'.
	236	# The STM32F10xxx has two serially connected JTAG TAPs, the
	237	# boundary scan tap (5 bits) and the Cortex-M3 TAP (4 bits).
	238	# See UM 31.5 "STM32F10xxx JTAG TAP connection" for details.
	239	self.state = ir.get(val[:-1][-4:], ['UNKNOWN', 0])[0]
	240	bstap_ir = ir.get(val[:-1][:4], ['UNKNOWN', 0])[0]
	241	self.putf(5, 8, [1, ['IR (BS TAP): ' + bstap_ir]])
	242	self.putf(1, 4, [1, ['IR (M3 TAP): ' + self.state]])
	243	self.putf(0, 0, [1, ['Reserved (BS TAP)', 'BS', 'B']])
	244	self.putx([2, ['IR: %s' % self.state]])
	245	elif self.state == 'BYPASS':
	246	# Here we're interested in incoming bits (TDI).
	247	if cmd != 'DR TDI':
	248	return
	249	handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
	250	handle_reg(cmd, val)
	251	self.state = 'IDLE'
	252	elif self.state in ('IDCODE', 'ABORT', 'UNKNOWN'):
	253	# Here we're interested in outgoing bits (TDO).
	254	if cmd != 'DR TDO':
	255	return
	256	handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
	257	handle_reg(cmd, val)
	258	self.state = 'IDLE'
	259	elif self.state in ('DPACC', 'APACC'):
	260	# Here we're interested in incoming and outgoing bits (TDI/TDO).
	261	if cmd not in ('DR TDI', 'DR TDO'):
	262	return
	263	handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
	264	handle_reg(cmd, val)
	265	if cmd == 'DR TDO': # Assumes 'DR TDI' comes before 'DR TDO'.
	266	self.state = 'IDLE'