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f44d2db2 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
f44d2db2 | 3 | ## |
0bb7bcf3 | 4 | ## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de> |
f44d2db2 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
677d597b | 21 | import sigrokdecode as srd |
f44d2db2 | 22 | |
4cace3b8 | 23 | ''' |
c515eed7 | 24 | OUTPUT_PYTHON format: |
4cace3b8 UH |
25 | |
26 | UART packet: | |
27 | [<packet-type>, <rxtx>, <packet-data>] | |
28 | ||
29 | This is the list of <packet-type>s and their respective <packet-data>: | |
30 | - 'STARTBIT': The data is the (integer) value of the start bit (0/1). | |
31 | - 'DATA': The data is the (integer) value of the UART data. Valid values | |
32 | range from 0 to 512 (as the data can be up to 9 bits in size). | |
4aedd5b8 | 33 | - 'DATABITS': List of data bits and their ss/es numbers. |
4cace3b8 UH |
34 | - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1). |
35 | - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1). | |
36 | - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1). | |
37 | - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1). | |
38 | - 'PARITY ERROR': The data is a tuple with two entries. The first one is | |
39 | the expected parity value, the second is the actual parity value. | |
40 | - TODO: Frame error? | |
41 | ||
42 | The <rxtx> field is 0 for RX packets, 1 for TX packets. | |
43 | ''' | |
44 | ||
97cca21f UH |
45 | # Used for differentiating between the two data directions. |
46 | RX = 0 | |
47 | TX = 1 | |
48 | ||
f44d2db2 UH |
49 | # Given a parity type to check (odd, even, zero, one), the value of the |
50 | # parity bit, the value of the data, and the length of the data (5-9 bits, | |
51 | # usually 8 bits) return True if the parity is correct, False otherwise. | |
a7fc4c34 | 52 | # 'none' is _not_ allowed as value for 'parity_type'. |
f44d2db2 UH |
53 | def parity_ok(parity_type, parity_bit, data, num_data_bits): |
54 | ||
55 | # Handle easy cases first (parity bit is always 1 or 0). | |
a7fc4c34 | 56 | if parity_type == 'zero': |
f44d2db2 | 57 | return parity_bit == 0 |
a7fc4c34 | 58 | elif parity_type == 'one': |
f44d2db2 UH |
59 | return parity_bit == 1 |
60 | ||
61 | # Count number of 1 (high) bits in the data (and the parity bit itself!). | |
ac941bf9 | 62 | ones = bin(data).count('1') + parity_bit |
f44d2db2 UH |
63 | |
64 | # Check for odd/even parity. | |
a7fc4c34 | 65 | if parity_type == 'odd': |
ac941bf9 | 66 | return (ones % 2) == 1 |
a7fc4c34 | 67 | elif parity_type == 'even': |
ac941bf9 | 68 | return (ones % 2) == 0 |
f44d2db2 UH |
69 | else: |
70 | raise Exception('Invalid parity type: %d' % parity_type) | |
71 | ||
677d597b | 72 | class Decoder(srd.Decoder): |
a2c2afd9 | 73 | api_version = 1 |
f44d2db2 UH |
74 | id = 'uart' |
75 | name = 'UART' | |
3d3da57d | 76 | longname = 'Universal Asynchronous Receiver/Transmitter' |
a465436e | 77 | desc = 'Asynchronous, serial bus.' |
f44d2db2 UH |
78 | license = 'gplv2+' |
79 | inputs = ['logic'] | |
80 | outputs = ['uart'] | |
3dd546c1 UH |
81 | probes = [] |
82 | optional_probes = [ | |
f44d2db2 UH |
83 | # Allow specifying only one of the signals, e.g. if only one data |
84 | # direction exists (or is relevant). | |
29ed0f4c UH |
85 | {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, |
86 | {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, | |
87 | ] | |
f44d2db2 | 88 | options = { |
97cca21f | 89 | 'baudrate': ['Baud rate', 115200], |
f44d2db2 | 90 | 'num_data_bits': ['Data bits', 8], # Valid: 5-9. |
a7fc4c34 UH |
91 | 'parity_type': ['Parity type', 'none'], |
92 | 'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported? | |
93 | 'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5. | |
94 | 'bit_order': ['Bit order', 'lsb-first'], | |
3006c663 | 95 | 'format': ['Data format', 'ascii'], # ascii/dec/hex/oct/bin |
f44d2db2 | 96 | # TODO: Options to invert the signal(s). |
f44d2db2 | 97 | } |
e97b6ef5 | 98 | annotations = [ |
2ce20a91 UH |
99 | ['rx-data', 'RX data'], |
100 | ['tx-data', 'TX data'], | |
4e3b276a UH |
101 | ['rx-start', 'RX start bits'], |
102 | ['tx-start', 'TX start bits'], | |
103 | ['rx-parity-ok', 'RX parity OK bits'], | |
104 | ['tx-parity-ok', 'TX parity OK bits'], | |
105 | ['rx-parity-err', 'RX parity error bits'], | |
106 | ['tx-parity-err', 'TX parity error bits'], | |
107 | ['rx-stop', 'RX stop bits'], | |
108 | ['tx-stop', 'TX stop bits'], | |
2ce20a91 UH |
109 | ['rx-warnings', 'RX warnings'], |
110 | ['tx-warnings', 'TX warnings'], | |
4aedd5b8 UH |
111 | ['rx-data-bits', 'RX data bits'], |
112 | ['tx-data-bits', 'TX data bits'], | |
1bb57ab8 | 113 | ] |
2ce20a91 | 114 | annotation_rows = ( |
4e3b276a | 115 | ('rx-data', 'RX', (0, 2, 4, 6, 8)), |
4aedd5b8 | 116 | ('rx-data-bits', 'RX bits', (12,)), |
4e3b276a | 117 | ('rx-warnings', 'RX warnings', (10,)), |
4aedd5b8 UH |
118 | ('tx-data', 'TX', (1, 3, 5, 7, 9)), |
119 | ('tx-data-bits', 'TX bits', (13,)), | |
4e3b276a | 120 | ('tx-warnings', 'TX warnings', (11,)), |
2ce20a91 | 121 | ) |
0bb7bcf3 UH |
122 | binary = ( |
123 | ('rx', 'RX dump'), | |
124 | ('tx', 'TX dump'), | |
125 | ('rxtx', 'RX/TX dump'), | |
126 | ) | |
f44d2db2 | 127 | |
97cca21f | 128 | def putx(self, rxtx, data): |
15ac6604 UH |
129 | s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) |
130 | self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data) | |
131 | ||
4aedd5b8 UH |
132 | def putpx(self, rxtx, data): |
133 | s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) | |
134 | self.put(s - halfbit, self.samplenum + halfbit, self.out_python, data) | |
135 | ||
15ac6604 UH |
136 | def putg(self, data): |
137 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
138 | self.put(s - halfbit, s + halfbit, self.out_ann, data) | |
139 | ||
140 | def putp(self, data): | |
141 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
c515eed7 | 142 | self.put(s - halfbit, s + halfbit, self.out_python, data) |
97cca21f | 143 | |
0bb7bcf3 UH |
144 | def putbin(self, rxtx, data): |
145 | s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) | |
146 | self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data) | |
147 | ||
f44d2db2 | 148 | def __init__(self, **kwargs): |
f372d597 | 149 | self.samplerate = None |
f44d2db2 | 150 | self.samplenum = 0 |
97cca21f UH |
151 | self.frame_start = [-1, -1] |
152 | self.startbit = [-1, -1] | |
153 | self.cur_data_bit = [0, 0] | |
154 | self.databyte = [0, 0] | |
1ccef461 | 155 | self.paritybit = [-1, -1] |
97cca21f UH |
156 | self.stopbit1 = [-1, -1] |
157 | self.startsample = [-1, -1] | |
2b716038 | 158 | self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] |
83be7b83 UH |
159 | self.oldbit = [1, 1] |
160 | self.oldpins = [1, 1] | |
4aedd5b8 | 161 | self.databits = [[], []] |
f44d2db2 | 162 | |
f372d597 | 163 | def start(self): |
c515eed7 | 164 | self.out_python = self.register(srd.OUTPUT_PYTHON) |
0bb7bcf3 | 165 | self.out_bin = self.register(srd.OUTPUT_BINARY) |
be465111 | 166 | self.out_ann = self.register(srd.OUTPUT_ANN) |
f44d2db2 | 167 | |
f372d597 BV |
168 | def metadata(self, key, value): |
169 | if key == srd.SRD_CONF_SAMPLERATE: | |
170 | self.samplerate = value; | |
171 | # The width of one UART bit in number of samples. | |
172 | self.bit_width = float(self.samplerate) / float(self.options['baudrate']) | |
f44d2db2 | 173 | |
f44d2db2 | 174 | # Return true if we reached the middle of the desired bit, false otherwise. |
97cca21f | 175 | def reached_bit(self, rxtx, bitnum): |
f44d2db2 UH |
176 | # bitpos is the samplenumber which is in the middle of the |
177 | # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit | |
178 | # (if used) or the first stop bit, and so on). | |
97cca21f | 179 | bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0) |
f44d2db2 UH |
180 | bitpos += bitnum * self.bit_width |
181 | if self.samplenum >= bitpos: | |
182 | return True | |
183 | return False | |
184 | ||
97cca21f UH |
185 | def reached_bit_last(self, rxtx, bitnum): |
186 | bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width) | |
f44d2db2 UH |
187 | if self.samplenum >= bitpos: |
188 | return True | |
189 | return False | |
190 | ||
97cca21f | 191 | def wait_for_start_bit(self, rxtx, old_signal, signal): |
f44d2db2 UH |
192 | # The start bit is always 0 (low). As the idle UART (and the stop bit) |
193 | # level is 1 (high), the beginning of a start bit is a falling edge. | |
194 | if not (old_signal == 1 and signal == 0): | |
195 | return | |
196 | ||
197 | # Save the sample number where the start bit begins. | |
97cca21f | 198 | self.frame_start[rxtx] = self.samplenum |
f44d2db2 | 199 | |
2b716038 | 200 | self.state[rxtx] = 'GET START BIT' |
f44d2db2 | 201 | |
97cca21f | 202 | def get_start_bit(self, rxtx, signal): |
f44d2db2 | 203 | # Skip samples until we're in the middle of the start bit. |
97cca21f | 204 | if not self.reached_bit(rxtx, 0): |
1bb57ab8 | 205 | return |
f44d2db2 | 206 | |
97cca21f | 207 | self.startbit[rxtx] = signal |
f44d2db2 | 208 | |
5cc4b6a0 | 209 | # The startbit must be 0. If not, we report an error. |
97cca21f | 210 | if self.startbit[rxtx] != 0: |
15ac6604 | 211 | self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) |
5cc4b6a0 | 212 | # TODO: Abort? Ignore rest of the frame? |
f44d2db2 | 213 | |
97cca21f UH |
214 | self.cur_data_bit[rxtx] = 0 |
215 | self.databyte[rxtx] = 0 | |
216 | self.startsample[rxtx] = -1 | |
f44d2db2 | 217 | |
2b716038 | 218 | self.state[rxtx] = 'GET DATA BITS' |
f44d2db2 | 219 | |
15ac6604 | 220 | self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) |
2ce20a91 | 221 | self.putg([rxtx + 2, ['Start bit', 'Start', 'S']]) |
f44d2db2 | 222 | |
97cca21f | 223 | def get_data_bits(self, rxtx, signal): |
f44d2db2 | 224 | # Skip samples until we're in the middle of the desired data bit. |
97cca21f | 225 | if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1): |
1bb57ab8 | 226 | return |
f44d2db2 | 227 | |
15ac6604 | 228 | # Save the sample number of the middle of the first data bit. |
97cca21f UH |
229 | if self.startsample[rxtx] == -1: |
230 | self.startsample[rxtx] = self.samplenum | |
f44d2db2 UH |
231 | |
232 | # Get the next data bit in LSB-first or MSB-first fashion. | |
a7fc4c34 | 233 | if self.options['bit_order'] == 'lsb-first': |
97cca21f | 234 | self.databyte[rxtx] >>= 1 |
fd4aa8aa UH |
235 | self.databyte[rxtx] |= \ |
236 | (signal << (self.options['num_data_bits'] - 1)) | |
a7fc4c34 | 237 | elif self.options['bit_order'] == 'msb-first': |
97cca21f UH |
238 | self.databyte[rxtx] <<= 1 |
239 | self.databyte[rxtx] |= (signal << 0) | |
f44d2db2 | 240 | else: |
a7fc4c34 | 241 | raise Exception('Invalid bit order value: %s', |
4a04ece4 | 242 | self.options['bit_order']) |
f44d2db2 | 243 | |
4aedd5b8 UH |
244 | self.putg([rxtx + 12, ['%d' % signal]]) |
245 | ||
246 | # Store individual data bits and their start/end samplenumbers. | |
247 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
248 | self.databits[rxtx].append([signal, s - halfbit, s + halfbit]) | |
249 | ||
f44d2db2 | 250 | # Return here, unless we already received all data bits. |
4a04ece4 | 251 | if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1: |
97cca21f | 252 | self.cur_data_bit[rxtx] += 1 |
1bb57ab8 | 253 | return |
f44d2db2 | 254 | |
2b716038 | 255 | self.state[rxtx] = 'GET PARITY BIT' |
f44d2db2 | 256 | |
4aedd5b8 UH |
257 | self.putpx(rxtx, ['DATABITS', rxtx, self.databits[rxtx]]) |
258 | self.putpx(rxtx, ['DATA', rxtx, self.databyte[rxtx]]) | |
f44d2db2 | 259 | |
3006c663 UH |
260 | b, f = self.databyte[rxtx], self.options['format'] |
261 | if f == 'ascii': | |
e0a0123d | 262 | c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b |
8705ddc8 | 263 | self.putx(rxtx, [rxtx, [c]]) |
3006c663 | 264 | elif f == 'dec': |
6d6b32d6 | 265 | self.putx(rxtx, [rxtx, [str(b)]]) |
3006c663 | 266 | elif f == 'hex': |
6d6b32d6 | 267 | self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]]) |
3006c663 | 268 | elif f == 'oct': |
6d6b32d6 | 269 | self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]]) |
3006c663 | 270 | elif f == 'bin': |
6d6b32d6 | 271 | self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]]) |
3006c663 UH |
272 | else: |
273 | raise Exception('Invalid data format option: %s' % f) | |
f44d2db2 | 274 | |
0bb7bcf3 UH |
275 | self.putbin(rxtx, (rxtx, bytes([b]))) |
276 | self.putbin(rxtx, (2, bytes([b]))) | |
277 | ||
4aedd5b8 UH |
278 | self.databits = [[], []] |
279 | ||
97cca21f | 280 | def get_parity_bit(self, rxtx, signal): |
f44d2db2 | 281 | # If no parity is used/configured, skip to the next state immediately. |
a7fc4c34 | 282 | if self.options['parity_type'] == 'none': |
2b716038 | 283 | self.state[rxtx] = 'GET STOP BITS' |
1bb57ab8 | 284 | return |
f44d2db2 UH |
285 | |
286 | # Skip samples until we're in the middle of the parity bit. | |
4a04ece4 | 287 | if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1): |
1bb57ab8 | 288 | return |
f44d2db2 | 289 | |
97cca21f | 290 | self.paritybit[rxtx] = signal |
f44d2db2 | 291 | |
2b716038 | 292 | self.state[rxtx] = 'GET STOP BITS' |
f44d2db2 | 293 | |
ac941bf9 | 294 | if parity_ok(self.options['parity_type'], self.paritybit[rxtx], |
4a04ece4 | 295 | self.databyte[rxtx], self.options['num_data_bits']): |
15ac6604 | 296 | self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) |
2ce20a91 | 297 | self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']]) |
f44d2db2 | 298 | else: |
61132abd | 299 | # TODO: Return expected/actual parity values. |
15ac6604 | 300 | self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... |
4e3b276a | 301 | self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']]) |
f44d2db2 UH |
302 | |
303 | # TODO: Currently only supports 1 stop bit. | |
97cca21f | 304 | def get_stop_bits(self, rxtx, signal): |
f44d2db2 | 305 | # Skip samples until we're in the middle of the stop bit(s). |
a7fc4c34 | 306 | skip_parity = 0 if self.options['parity_type'] == 'none' else 1 |
4a04ece4 UH |
307 | b = self.options['num_data_bits'] + 1 + skip_parity |
308 | if not self.reached_bit(rxtx, b): | |
1bb57ab8 | 309 | return |
f44d2db2 | 310 | |
97cca21f | 311 | self.stopbit1[rxtx] = signal |
f44d2db2 | 312 | |
5cc4b6a0 | 313 | # Stop bits must be 1. If not, we report an error. |
97cca21f | 314 | if self.stopbit1[rxtx] != 1: |
15ac6604 | 315 | self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) |
4e3b276a | 316 | self.putg([rxtx + 8, ['Frame error', 'Frame err', 'FE']]) |
5cc4b6a0 | 317 | # TODO: Abort? Ignore the frame? Other? |
f44d2db2 | 318 | |
2b716038 | 319 | self.state[rxtx] = 'WAIT FOR START BIT' |
f44d2db2 | 320 | |
15ac6604 | 321 | self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) |
2ce20a91 | 322 | self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) |
f44d2db2 | 323 | |
decde15e | 324 | def decode(self, ss, es, data): |
f372d597 BV |
325 | if self.samplerate is None: |
326 | raise Exception("Cannot decode without samplerate.") | |
2fcd7c22 UH |
327 | for (self.samplenum, pins) in data: |
328 | ||
b0827236 UH |
329 | # Note: Ignoring identical samples here for performance reasons |
330 | # is not possible for this PD, at least not in the current state. | |
331 | # if self.oldpins == pins: | |
332 | # continue | |
2fcd7c22 | 333 | self.oldpins, (rx, tx) = pins, pins |
f44d2db2 | 334 | |
3dd546c1 UH |
335 | # Either RX or TX (but not both) can be omitted. |
336 | has_pin = [rx in (0, 1), tx in (0, 1)] | |
337 | if has_pin == [False, False]: | |
338 | raise Exception('Either TX or RX (or both) pins required.') | |
339 | ||
f44d2db2 | 340 | # State machine. |
97cca21f | 341 | for rxtx in (RX, TX): |
3dd546c1 UH |
342 | # Don't try to handle RX (or TX) if not supplied. |
343 | if not has_pin[rxtx]: | |
344 | continue | |
345 | ||
97cca21f UH |
346 | signal = rx if (rxtx == RX) else tx |
347 | ||
2b716038 | 348 | if self.state[rxtx] == 'WAIT FOR START BIT': |
97cca21f | 349 | self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal) |
2b716038 | 350 | elif self.state[rxtx] == 'GET START BIT': |
97cca21f | 351 | self.get_start_bit(rxtx, signal) |
2b716038 | 352 | elif self.state[rxtx] == 'GET DATA BITS': |
97cca21f | 353 | self.get_data_bits(rxtx, signal) |
2b716038 | 354 | elif self.state[rxtx] == 'GET PARITY BIT': |
97cca21f | 355 | self.get_parity_bit(rxtx, signal) |
2b716038 | 356 | elif self.state[rxtx] == 'GET STOP BITS': |
97cca21f UH |
357 | self.get_stop_bits(rxtx, signal) |
358 | else: | |
0eeeb544 | 359 | raise Exception('Invalid state: %s' % self.state[rxtx]) |
97cca21f UH |
360 | |
361 | # Save current RX/TX values for the next round. | |
362 | self.oldbit[rxtx] = signal | |
f44d2db2 | 363 |