[libsigrokdecode.git] / decoders / rtc8564 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

# Return the specified BCD number (max. 8 bits) as integer.
def bcd2int(b):
    return (b & 0x0f) + ((b >> 4) * 10)

class Decoder(srd.Decoder):
    api_version = 1
    id = 'rtc8564'
    name = 'RTC-8564'
    longname = 'Epson RTC-8564 JE/NB'
    desc = 'Realtime clock module protocol.'
    license = 'gplv2+'
    inputs = ['i2c']
    outputs = ['rtc8564']
    probes = []
    optional_probes = [
        {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
        {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
        {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
    ]
    options = {}
    annotations = [
        ['reg-0x00', 'Register 0x00'],
        ['reg-0x01', 'Register 0x01'],
        ['reg-0x02', 'Register 0x02'],
        ['reg-0x03', 'Register 0x03'],
        ['reg-0x04', 'Register 0x04'],
        ['reg-0x05', 'Register 0x05'],
        ['reg-0x06', 'Register 0x06'],
        ['reg-0x07', 'Register 0x07'],
        ['reg-0x08', 'Register 0x08'],
        ['read', 'Read date/time'],
        ['write', 'Write date/time'],
        ['bit-reserved', 'Reserved bit'],
        ['bit-vl', 'VL bit'],
        ['bit-century', 'Century bit'],
        ['reg-read', 'Register read'],
        ['reg-write', 'Register write'],
    ]
    annotation_rows = (
        ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
        ('regs', 'Register access', (14, 15)),
        ('date-time', 'Date/time', (9, 10)),
    )

    def __init__(self, **kwargs):
        self.state = 'IDLE'
        self.hours = -1
        self.minutes = -1
        self.seconds = -1
        self.days = -1
        self.weekdays = -1
        self.months = -1
        self.years = -1
        self.bits = []

    def start(self):
        # self.out_python = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss, self.es, self.out_ann, data)

    def putd(self, bit1, bit2, data):
        self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)

    def putr(self, bit):
        self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
                 [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])

    def handle_reg_0x00(self, b): # Control register 1
        pass

    def handle_reg_0x01(self, b): # Control register 2
        ti_tp = 1 if (b & (1 << 4)) else 0
        af = 1 if (b & (1 << 3)) else 0
        tf = 1 if (b & (1 << 2)) else 0
        aie = 1 if (b & (1 << 1)) else 0
        tie = 1 if (b & (1 << 0)) else 0

        ann = ''

        s = 'repeated' if ti_tp else 'single-shot'
        ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
               'events\n' % (ti_tp, s)
        s = '' if af else 'no '
        ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
        s = '' if tf else 'no '
        ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
        s = 'enabled' if aie else 'prohibited'
        ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
               'occurs\n' % (aie, s)
        s = 'enabled' if tie else 'prohibited'
        ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
               'event occurs\n' % (tie, s)

        self.putx([1, [ann]])

    def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
        vl = 1 if (b & (1 << 7)) else 0
        self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
                        'VL: %d' % vl, 'VL']])
        s = self.seconds = bcd2int(b & 0x7f)
        self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])

    def handle_reg_0x03(self, b): # Minutes
        self.putr(7)
        m = self.minutes = bcd2int(b & 0x7f)
        self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])

    def handle_reg_0x04(self, b): # Hours
        self.putr(7)
        self.putr(6)
        h = self.hours = bcd2int(b & 0x3f)
        self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']])

    def handle_reg_0x05(self, b): # Days
        self.putr(7)
        self.putr(6)
        d = self.days = bcd2int(b & 0x3f)
        self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']])

    def handle_reg_0x06(self, b): # Weekdays
        for i in (7, 6, 5, 4, 3):
            self.putr(i)
        w = self.weekdays = bcd2int(b & 0x07)
        self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']])

    def handle_reg_0x07(self, b): # Months / century bit
        c = 1 if (b & (1 << 7)) else 0
        self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c,
                              'Cent: %d' % c, 'C: %d' % c, 'C']])
        self.putr(6)
        self.putr(5)
        m = self.months = bcd2int(b & 0x1f)
        self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])

    def handle_reg_0x08(self, b): # Years
        y = self.years = bcd2int(b & 0xff)
        self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']])

    def handle_reg_0x09(self, b): # Alarm, minute
        pass

    def handle_reg_0x0a(self, b): # Alarm, hour
        pass

    def handle_reg_0x0b(self, b): # Alarm, day
        pass

    def handle_reg_0x0c(self, b): # Alarm, weekday
        pass

    def handle_reg_0x0d(self, b): # CLKOUT output
        pass

    def handle_reg_0x0e(self, b): # Timer setting
        pass

    def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
        pass

    def decode(self, ss, es, data):
        cmd, databyte = data

        # Collect the 'BITS' packet, then return. The next packet is
        # guaranteed to belong to these bits we just stored.
        if cmd == 'BITS':
            self.bits = databyte
            return

        # Store the start/end samples of this I²C packet.
        self.ss, self.es = ss, es

        # State machine.
        if self.state == 'IDLE':
            # Wait for an I²C START condition.
            if cmd != 'START':
                return
            self.state = 'GET SLAVE ADDR'
            self.block_start_sample = ss
        elif self.state == 'GET SLAVE ADDR':
            # Wait for an address write operation.
            # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
            if cmd != 'ADDRESS WRITE':
                return
            self.state = 'GET REG ADDR'
        elif self.state == 'GET REG ADDR':
            # Wait for a data write (master selects the slave register).
            if cmd != 'DATA WRITE':
                return
            self.reg = databyte
            self.state = 'WRITE RTC REGS'
        elif self.state == 'WRITE RTC REGS':
            # If we see a Repeated Start here, it's probably an RTC read.
            if cmd == 'START REPEAT':
                self.state = 'READ RTC REGS'
                return
            # Otherwise: Get data bytes until a STOP condition occurs.
            if cmd == 'DATA WRITE':
                r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
                self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
                                'WR %s' % s, 'WR', 'W']])
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                # TODO: Handle read/write of only parts of these items.
                d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.block_start_sample, es, self.out_ann,
                         [9, ['Write date/time: %s' % d, 'Write: %s' % d,
                              'W: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS':
            # Wait for an address read operation.
            # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
            if cmd == 'ADDRESS READ':
                self.state = 'READ RTC REGS2'
                return
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS2':
            if cmd == 'DATA READ':
                r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
                self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
                                'RR %s' % s, 'RR', 'R']])
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.block_start_sample, es, self.out_ann,
                         [10, ['Read date/time: %s' % d, 'Read: %s' % d,
                               'R: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO?
        else:
            raise Exception('Invalid state: %s' % self.state)
Commit	Line	Data
ed5f826a	1	##
50bd5d25	2	## This file is part of the libsigrokdecode project.
ed5f826a	3	##
6e256b1c	4	## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
ed5f826a UH	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
ed5f826a UH	21	import sigrokdecode as srd
ed5f826a UH	22
ed5f826a UH	23	# Return the specified BCD number (max. 8 bits) as integer.
	24	def bcd2int(b):
	25	return (b & 0x0f) + ((b >> 4) * 10)
	26
	27	class Decoder(srd.Decoder):
	28	api_version = 1
	29	id = 'rtc8564'
	30	name = 'RTC-8564'
	31	longname = 'Epson RTC-8564 JE/NB'
a465436e	32	desc = 'Realtime clock module protocol.'
ed5f826a UH	33	license = 'gplv2+'
	34	inputs = ['i2c']
	35	outputs = ['rtc8564']
	36	probes = []
b77614bc	37	optional_probes = [
847e488b UH	38	{'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
	39	{'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
	40	{'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
ed5f826a UH	41	]
	42	options = {}
	43	annotations = [
a4289441 UH	44	['reg-0x00', 'Register 0x00'],
	45	['reg-0x01', 'Register 0x01'],
	46	['reg-0x02', 'Register 0x02'],
	47	['reg-0x03', 'Register 0x03'],
	48	['reg-0x04', 'Register 0x04'],
	49	['reg-0x05', 'Register 0x05'],
	50	['reg-0x06', 'Register 0x06'],
	51	['reg-0x07', 'Register 0x07'],
	52	['reg-0x08', 'Register 0x08'],
	53	['read', 'Read date/time'],
	54	['write', 'Write date/time'],
09d09ace UH	55	['bit-reserved', 'Reserved bit'],
	56	['bit-vl', 'VL bit'],
	57	['bit-century', 'Century bit'],
	58	['reg-read', 'Register read'],
	59	['reg-write', 'Register write'],
ed5f826a	60	]
3161ab5a	61	annotation_rows = (
09d09ace UH	62	('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
09d09ace UH	63	('regs', 'Register access', (14, 15)),
3161ab5a UH	64	('date-time', 'Date/time', (9, 10)),
3161ab5a UH	65	)
ed5f826a UH	66
ed5f826a UH	67	def __init__(self, **kwargs):
2b716038	68	self.state = 'IDLE'
ed5f826a UH	69	self.hours = -1
	70	self.minutes = -1
	71	self.seconds = -1
	72	self.days = -1
3d190141	73	self.weekdays = -1
ed5f826a UH	74	self.months = -1
ed5f826a UH	75	self.years = -1
09d09ace	76	self.bits = []
ed5f826a	77
8915b346	78	def start(self):
c515eed7	79	# self.out_python = self.register(srd.OUTPUT_PYTHON)
be465111	80	self.out_ann = self.register(srd.OUTPUT_ANN)
ed5f826a	81
ed5f826a UH	82	def putx(self, data):
	83	self.put(self.ss, self.es, self.out_ann, data)
	84
09d09ace UH	85	def putd(self, bit1, bit2, data):
	86	self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
	87
	88	def putr(self, bit):
	89	self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
	90	[11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
	91
ed5f826a UH	92	def handle_reg_0x00(self, b): # Control register 1
	93	pass
	94
	95	def handle_reg_0x01(self, b): # Control register 2
	96	ti_tp = 1 if (b & (1 << 4)) else 0
	97	af = 1 if (b & (1 << 3)) else 0
	98	tf = 1 if (b & (1 << 2)) else 0
	99	aie = 1 if (b & (1 << 1)) else 0
	100	tie = 1 if (b & (1 << 0)) else 0
	101
	102	ann = ''
	103
	104	s = 'repeated' if ti_tp else 'single-shot'
	105	ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
	106	'events\n' % (ti_tp, s)
	107	s = '' if af else 'no '
	108	ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
	109	s = '' if tf else 'no '
	110	ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
	111	s = 'enabled' if aie else 'prohibited'
	112	ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
	113	'occurs\n' % (aie, s)
	114	s = 'enabled' if tie else 'prohibited'
	115	ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
	116	'event occurs\n' % (tie, s)
	117
a4289441	118	self.putx([1, [ann]])
ed5f826a	119
64134a4c	120	def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
ed5f826a	121	vl = 1 if (b & (1 << 7)) else 0
09d09ace	122	self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
bff3a0a0	123	'VL: %d' % vl, 'VL']])
09d09ace	124	s = self.seconds = bcd2int(b & 0x7f)
bff3a0a0	125	self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])
ed5f826a UH	126
ed5f826a UH	127	def handle_reg_0x03(self, b): # Minutes
09d09ace	128	self.putr(7)
6e256b1c	129	m = self.minutes = bcd2int(b & 0x7f)
bff3a0a0	130	self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])
ed5f826a UH	131
ed5f826a UH	132	def handle_reg_0x04(self, b): # Hours
09d09ace UH	133	self.putr(7)
09d09ace UH	134	self.putr(6)
6e256b1c	135	h = self.hours = bcd2int(b & 0x3f)
bff3a0a0	136	self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']])
ed5f826a UH	137
ed5f826a UH	138	def handle_reg_0x05(self, b): # Days
09d09ace UH	139	self.putr(7)
09d09ace UH	140	self.putr(6)
6e256b1c	141	d = self.days = bcd2int(b & 0x3f)
bff3a0a0	142	self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']])
ed5f826a	143
3d190141	144	def handle_reg_0x06(self, b): # Weekdays
09d09ace UH	145	for i in (7, 6, 5, 4, 3):
09d09ace UH	146	self.putr(i)
6e256b1c	147	w = self.weekdays = bcd2int(b & 0x07)
bff3a0a0	148	self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']])
ed5f826a	149
64134a4c	150	def handle_reg_0x07(self, b): # Months / century bit
64134a4c	151	c = 1 if (b & (1 << 7)) else 0
bff3a0a0 UH	152	self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c,
bff3a0a0 UH	153	'Cent: %d' % c, 'C: %d' % c, 'C']])
09d09ace UH	154	self.putr(6)
	155	self.putr(5)
	156	m = self.months = bcd2int(b & 0x1f)
bff3a0a0	157	self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])
ed5f826a UH	158
ed5f826a UH	159	def handle_reg_0x08(self, b): # Years
6e256b1c	160	y = self.years = bcd2int(b & 0xff)
bff3a0a0	161	self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']])
ed5f826a UH	162
	163	def handle_reg_0x09(self, b): # Alarm, minute
	164	pass
	165
	166	def handle_reg_0x0a(self, b): # Alarm, hour
	167	pass
	168
	169	def handle_reg_0x0b(self, b): # Alarm, day
	170	pass
	171
	172	def handle_reg_0x0c(self, b): # Alarm, weekday
	173	pass
	174
	175	def handle_reg_0x0d(self, b): # CLKOUT output
	176	pass
	177
	178	def handle_reg_0x0e(self, b): # Timer setting
	179	pass
	180
	181	def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
	182	pass
	183
	184	def decode(self, ss, es, data):
1b75abfd	185	cmd, databyte = data
ed5f826a	186
09d09ace UH	187	# Collect the 'BITS' packet, then return. The next packet is
	188	# guaranteed to belong to these bits we just stored.
	189	if cmd == 'BITS':
	190	self.bits = databyte
	191	return
	192
00197484	193	# Store the start/end samples of this I²C packet.
ed5f826a UH	194	self.ss, self.es = ss, es
	195
	196	# State machine.
2b716038	197	if self.state == 'IDLE':
00197484	198	# Wait for an I²C START condition.
ed5f826a UH	199	if cmd != 'START':
ed5f826a UH	200	return
2b716038	201	self.state = 'GET SLAVE ADDR'
ed5f826a	202	self.block_start_sample = ss
2b716038	203	elif self.state == 'GET SLAVE ADDR':
ed5f826a UH	204	# Wait for an address write operation.
	205	# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
	206	if cmd != 'ADDRESS WRITE':
	207	return
2b716038 UH	208	self.state = 'GET REG ADDR'
2b716038 UH	209	elif self.state == 'GET REG ADDR':
ed5f826a UH	210	# Wait for a data write (master selects the slave register).
	211	if cmd != 'DATA WRITE':
	212	return
	213	self.reg = databyte
2b716038 UH	214	self.state = 'WRITE RTC REGS'
2b716038 UH	215	elif self.state == 'WRITE RTC REGS':
ed5f826a UH	216	# If we see a Repeated Start here, it's probably an RTC read.
ed5f826a UH	217	if cmd == 'START REPEAT':
2b716038	218	self.state = 'READ RTC REGS'
ed5f826a UH	219	return
	220	# Otherwise: Get data bytes until a STOP condition occurs.
	221	if cmd == 'DATA WRITE':
09d09ace UH	222	r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
	223	self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
	224	'WR %s' % s, 'WR', 'W']])
ed5f826a UH	225	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	226	handle_reg(databyte)
	227	self.reg += 1
	228	# TODO: Check for NACK!
	229	elif cmd == 'STOP':
	230	# TODO: Handle read/write of only parts of these items.
	231	d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
	232	self.years, self.hours, self.minutes, self.seconds)
	233	self.put(self.block_start_sample, es, self.out_ann,
6e256b1c UH	234	[9, ['Write date/time: %s' % d, 'Write: %s' % d,
6e256b1c UH	235	'W: %s' % d]])
2b716038	236	self.state = 'IDLE'
ed5f826a UH	237	else:
ed5f826a UH	238	pass # TODO
2b716038	239	elif self.state == 'READ RTC REGS':
ed5f826a UH	240	# Wait for an address read operation.
	241	# TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
	242	if cmd == 'ADDRESS READ':
2b716038	243	self.state = 'READ RTC REGS2'
ed5f826a UH	244	return
ed5f826a UH	245	else:
e4f82268	246	pass # TODO
2b716038	247	elif self.state == 'READ RTC REGS2':
ed5f826a	248	if cmd == 'DATA READ':
09d09ace UH	249	r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
	250	self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
	251	'RR %s' % s, 'RR', 'R']])
ed5f826a UH	252	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	253	handle_reg(databyte)
	254	self.reg += 1
	255	# TODO: Check for NACK!
	256	elif cmd == 'STOP':
	257	d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
	258	self.years, self.hours, self.minutes, self.seconds)
	259	self.put(self.block_start_sample, es, self.out_ann,
6e256b1c UH	260	[10, ['Read date/time: %s' % d, 'Read: %s' % d,
6e256b1c UH	261	'R: %s' % d]])
2b716038	262	self.state = 'IDLE'
ed5f826a UH	263	else:
	264	pass # TODO?
	265	else:
0eeeb544	266	raise Exception('Invalid state: %s' % self.state)
ed5f826a	267