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d997c01a 1##
50bd5d25 2## This file is part of the libsigrokdecode project.
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3##
4## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
4539e9ca 17## along with this program; if not, see <http://www.gnu.org/licenses/>.
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18##
19
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20import sigrokdecode as srd
21
17160de7 22# Definitions of various bits in MXC6225XU registers.
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23status = {
24 # SH[1:0]
25 'sh': {
17160de7 26 0b00: 'none',
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27 0b01: 'shake left',
28 0b10: 'shake right',
29 0b11: 'undefined',
30 },
31 # ORI[1:0] and OR[1:0] (same format)
32 'ori': {
33 0b00: 'vertical in upright orientation',
34 0b01: 'rotated 90 degrees clockwise',
35 0b10: 'vertical in inverted orientation',
36 0b11: 'rotated 90 degrees counterclockwise',
37 },
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38 # SHTH[1:0]
39 'shth': {
40 0b00: '0.5g',
41 0b01: '1.0g',
42 0b10: '1.5g',
43 0b11: '2.0g',
44 },
45 # SHC[1:0]
46 'shc': {
47 0b00: '16',
48 0b01: '32',
49 0b10: '64',
50 0b11: '128',
51 },
52 # ORC[1:0]
53 'orc': {
54 0b00: '16',
55 0b01: '32',
56 0b10: '64',
57 0b11: '128',
58 },
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59}
60
61class Decoder(srd.Decoder):
12851357 62 api_version = 2
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63 id = 'mxc6225xu'
64 name = 'MXC6225XU'
65 longname = 'MEMSIC MXC6225XU'
a465436e 66 desc = 'Digital Thermal Orientation Sensor (DTOS) protocol.'
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67 license = 'gplv2+'
68 inputs = ['i2c']
69 outputs = ['mxc6225xu']
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70 annotations = (
71 ('text', 'Human-readable text'),
72 )
d997c01a 73
92b7b49f 74 def __init__(self):
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75 self.state = 'IDLE'
76
8915b346 77 def start(self):
be465111 78 self.out_ann = self.register(srd.OUTPUT_ANN)
d997c01a 79
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80 def putx(self, data):
81 self.put(self.ss, self.es, self.out_ann, data)
82
83 def handle_reg_0x00(self, b):
84 # XOUT: 8-bit x-axis acceleration output.
85 # Data is in 2's complement, values range from -128 to 127.
17160de7 86 self.putx([0, ['XOUT: %d' % b]])
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87
88 def handle_reg_0x01(self, b):
89 # YOUT: 8-bit y-axis acceleration output.
90 # Data is in 2's complement, values range from -128 to 127.
17160de7 91 self.putx([0, ['YOUT: %d' % b]])
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92
93 def handle_reg_0x02(self, b):
94 # STATUS: Orientation and shake status.
95
17160de7 96 # Bits[7:7]: INT
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97 int_val = (b >> 7) & 1
98 s = 'unchanged and no' if (int_val == 0) else 'changed or'
868fd207 99 ann = 'INT = %d: Orientation %s shake event occurred\n' % (int_val, s)
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100
101 # Bits[6:5]: SH[1:0]
102 sh = (((b >> 6) & 1) << 1) | ((b >> 5) & 1)
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103 ann += 'SH[1:0] = %s: Shake event: %s\n' % \
104 (bin(sh)[2:], status['sh'][sh])
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105
106 # Bits[4:4]: TILT
17160de7 107 tilt = (b >> 4) & 1
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108 s = '' if (tilt == 0) else 'not '
109 ann += 'TILT = %d: Orientation measurement is %svalid\n' % (tilt, s)
110
111 # Bits[3:2]: ORI[1:0]
112 ori = (((b >> 3) & 1) << 1) | ((b >> 2) & 1)
113 ann += 'ORI[1:0] = %s: %s\n' % (bin(ori)[2:], status['ori'][ori])
114
115 # Bits[1:0]: OR[1:0]
116 or_val = (((b >> 1) & 1) << 1) | ((b >> 0) & 1)
117 ann += 'OR[1:0] = %s: %s\n' % (bin(or_val)[2:], status['ori'][or_val])
118
119 # ann += 'b = %s\n' % (bin(b))
120
121 self.putx([0, [ann]])
122
123 def handle_reg_0x03(self, b):
124 # DETECTION: Powerdown, orientation and shake detection parameters.
125 # Note: This is a write-only register.
126
17160de7 127 # Bits[7:7]: PD
d997c01a 128 pd = (b >> 7) & 1
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129 s = 'Do not power down' if (pd == 0) else 'Power down'
130 ann = 'PD = %d: %s the device (into a low-power state)\n' % (pd, s)
d997c01a 131
17160de7 132 # Bits[6:6]: SHM
d997c01a 133 shm = (b >> 6) & 1
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134 ann = 'SHM = %d: Set shake mode to %d\n' % (shm, shm)
135
136 # Bits[5:4]: SHTH[1:0]
137 shth = (((b >> 5) & 1) << 1) | ((b >> 4) & 1)
138 ann += 'SHTH[1:0] = %s: Set shake threshold to %s\n' \
139 % (bin(shth)[2:], status['shth'][shth])
d997c01a 140
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141 # Bits[3:2]: SHC[1:0]
142 shc = (((b >> 3) & 1) << 1) | ((b >> 2) & 1)
143 ann += 'SHC[1:0] = %s: Set shake count to %s readings\n' \
144 % (bin(shc)[2:], status['shc'][shc])
145
146 # Bits[1:0]: ORC[1:0]
147 orc = (((b >> 1) & 1) << 1) | ((b >> 0) & 1)
148 ann += 'ORC[1:0] = %s: Set orientation count to %s readings\n' \
149 % (bin(orc)[2:], status['orc'][orc])
150
151 self.putx([0, [ann]])
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152
153 # TODO: Fixup, this is copy-pasted from another PD.
17160de7 154 # TODO: Handle/check the ACKs/NACKs.
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155 def decode(self, ss, es, data):
156 cmd, databyte = data
157
31f1a296 158 # Store the start/end samples of this I²C packet.
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159 self.ss, self.es = ss, es
160
161 # State machine.
162 if self.state == 'IDLE':
31f1a296 163 # Wait for an I²C START condition.
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164 if cmd != 'START':
165 return
166 self.state = 'GET SLAVE ADDR'
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167 elif self.state == 'GET SLAVE ADDR':
168 # Wait for an address write operation.
17160de7 169 # TODO: We should only handle packets to the slave(?)
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170 if cmd != 'ADDRESS WRITE':
171 return
172 self.state = 'GET REG ADDR'
173 elif self.state == 'GET REG ADDR':
174 # Wait for a data write (master selects the slave register).
175 if cmd != 'DATA WRITE':
176 return
177 self.reg = databyte
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178 self.state = 'WRITE REGS'
179 elif self.state == 'WRITE REGS':
180 # If we see a Repeated Start here, it's a multi-byte read.
d997c01a 181 if cmd == 'START REPEAT':
17160de7 182 self.state = 'READ REGS'
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183 return
184 # Otherwise: Get data bytes until a STOP condition occurs.
185 if cmd == 'DATA WRITE':
186 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
187 handle_reg(databyte)
188 self.reg += 1
189 # TODO: Check for NACK!
190 elif cmd == 'STOP':
191 # TODO
192 self.state = 'IDLE'
193 else:
194 pass # TODO
17160de7 195 elif self.state == 'READ REGS':
d997c01a 196 # Wait for an address read operation.
17160de7 197 # TODO: We should only handle packets to the slave(?)
d997c01a 198 if cmd == 'ADDRESS READ':
17160de7 199 self.state = 'READ REGS2'
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200 return
201 else:
202 pass # TODO
17160de7 203 elif self.state == 'READ REGS2':
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204 if cmd == 'DATA READ':
205 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
206 handle_reg(databyte)
207 self.reg += 1
208 # TODO: Check for NACK!
209 elif cmd == 'STOP':
210 # TODO
211 self.state = 'IDLE'
212 else:
213 pass # TODO?