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0588ed70 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
0588ed70 | 3 | ## |
592f355b | 4 | ## Copyright (C) 2010-2016 Uwe Hermann <uwe@hermann-uwe.de> |
0588ed70 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
0588ed70 UH |
18 | ## |
19 | ||
0588ed70 | 20 | # TODO: Look into arbitration, collision detection, clock synchronisation, etc. |
0588ed70 UH |
21 | # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). |
22 | # TODO: Implement support for detecting various bus errors. | |
23fb2e12 | 23 | |
647aba6a | 24 | from common.srdhelper import bitpack_msb |
677d597b | 25 | import sigrokdecode as srd |
b2c19614 | 26 | |
f1428c4c | 27 | ''' |
c515eed7 | 28 | OUTPUT_PYTHON format: |
f1428c4c | 29 | |
bf69977d UH |
30 | Packet: |
31 | [<ptype>, <pdata>] | |
f1428c4c | 32 | |
bf69977d | 33 | <ptype>: |
f1428c4c UH |
34 | - 'START' (START condition) |
35 | - 'START REPEAT' (Repeated START condition) | |
36 | - 'ADDRESS READ' (Slave address, read) | |
37 | - 'ADDRESS WRITE' (Slave address, write) | |
38 | - 'DATA READ' (Data, read) | |
39 | - 'DATA WRITE' (Data, write) | |
40 | - 'STOP' (STOP condition) | |
41 | - 'ACK' (ACK bit) | |
42 | - 'NACK' (NACK bit) | |
bf69977d | 43 | - 'BITS' (<pdata>: list of data/address bits and their ss/es numbers) |
f1428c4c | 44 | |
bf69977d | 45 | <pdata> is the data or address byte associated with the 'ADDRESS*' and 'DATA*' |
f1428c4c UH |
46 | command. Slave addresses do not include bit 0 (the READ/WRITE indication bit). |
47 | For example, a slave address field could be 0x51 (instead of 0xa2). | |
bf69977d | 48 | For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <pdata> is None. |
f1428c4c UH |
49 | ''' |
50 | ||
01416b98 GS |
51 | # Meaning of table items: |
52 | # command -> [annotation class, annotation text in order of decreasing length] | |
1541976f | 53 | proto = { |
01416b98 GS |
54 | 'START': [0, 'Start', 'S'], |
55 | 'START REPEAT': [1, 'Start repeat', 'Sr'], | |
56 | 'STOP': [2, 'Stop', 'P'], | |
57 | 'ACK': [3, 'ACK', 'A'], | |
58 | 'NACK': [4, 'NACK', 'N'], | |
59 | 'BIT': [5, '{b:1d}'], | |
60 | 'ADDRESS READ': [6, 'Address read: {b:02X}', 'AR: {b:02X}', '{b:02X}'], | |
61 | 'ADDRESS WRITE': [7, 'Address write: {b:02X}', 'AW: {b:02X}', '{b:02X}'], | |
62 | 'DATA READ': [8, 'Data read: {b:02X}', 'DR: {b:02X}', '{b:02X}'], | |
63 | 'DATA WRITE': [9, 'Data write: {b:02X}', 'DW: {b:02X}', '{b:02X}'], | |
15969949 | 64 | } |
e5080882 | 65 | |
677d597b | 66 | class Decoder(srd.Decoder): |
592f355b | 67 | api_version = 3 |
67e847fd | 68 | id = 'i2c' |
ab4aa33c | 69 | name = 'I²C' |
9a12a6e7 | 70 | longname = 'Inter-Integrated Circuit' |
a465436e | 71 | desc = 'Two-wire, multi-master, serial bus.' |
f39d2404 UH |
72 | license = 'gplv2+' |
73 | inputs = ['logic'] | |
74 | outputs = ['i2c'] | |
d6d8a8a4 | 75 | tags = ['Embedded/industrial'] |
6a15597a | 76 | channels = ( |
bc5f5a43 BV |
77 | {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'}, |
78 | {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, | |
da9bcbd9 | 79 | ) |
84c1c0b5 BV |
80 | options = ( |
81 | {'id': 'address_format', 'desc': 'Displayed slave address format', | |
82 | 'default': 'shifted', 'values': ('shifted', 'unshifted')}, | |
83 | ) | |
da9bcbd9 BV |
84 | annotations = ( |
85 | ('start', 'Start condition'), | |
86 | ('repeat-start', 'Repeat start condition'), | |
87 | ('stop', 'Stop condition'), | |
88 | ('ack', 'ACK'), | |
89 | ('nack', 'NACK'), | |
90 | ('bit', 'Data/address bit'), | |
91 | ('address-read', 'Address read'), | |
92 | ('address-write', 'Address write'), | |
93 | ('data-read', 'Data read'), | |
94 | ('data-write', 'Data write'), | |
e144452b | 95 | ('warning', 'Warning'), |
da9bcbd9 | 96 | ) |
de038c47 UH |
97 | annotation_rows = ( |
98 | ('bits', 'Bits', (5,)), | |
e144452b | 99 | ('addr-data', 'Address/data', (0, 1, 2, 3, 4, 6, 7, 8, 9)), |
de038c47 UH |
100 | ('warnings', 'Warnings', (10,)), |
101 | ) | |
a929afa6 | 102 | binary = ( |
5cb2cb02 BV |
103 | ('address-read', 'Address read'), |
104 | ('address-write', 'Address write'), | |
105 | ('data-read', 'Data read'), | |
106 | ('data-write', 'Data write'), | |
a929afa6 | 107 | ) |
0588ed70 | 108 | |
92b7b49f | 109 | def __init__(self): |
10aeb8ea GS |
110 | self.reset() |
111 | ||
112 | def reset(self): | |
8d2a9636 | 113 | self.samplerate = None |
486b19ce | 114 | self.ss = self.es = self.ss_byte = -1 |
14ba515b | 115 | self.is_write = None |
4f139c28 | 116 | self.rem_addr_bytes = None |
14ba515b | 117 | self.is_repeat_start = False |
2b716038 | 118 | self.state = 'FIND START' |
8d2a9636 BV |
119 | self.pdu_start = None |
120 | self.pdu_bits = 0 | |
14ba515b | 121 | self.data_bits = [] |
8d2a9636 BV |
122 | |
123 | def metadata(self, key, value): | |
124 | if key == srd.SRD_CONF_SAMPLERATE: | |
125 | self.samplerate = value | |
f39d2404 | 126 | |
8915b346 | 127 | def start(self): |
c515eed7 | 128 | self.out_python = self.register(srd.OUTPUT_PYTHON) |
8d2a9636 | 129 | self.out_ann = self.register(srd.OUTPUT_ANN) |
be6733ca | 130 | self.out_binary = self.register(srd.OUTPUT_BINARY) |
8d2a9636 BV |
131 | self.out_bitrate = self.register(srd.OUTPUT_META, |
132 | meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit')) | |
3643fc3f | 133 | |
d94ff143 | 134 | def putx(self, data): |
de038c47 | 135 | self.put(self.ss, self.es, self.out_ann, data) |
d94ff143 UH |
136 | |
137 | def putp(self, data): | |
de038c47 | 138 | self.put(self.ss, self.es, self.out_python, data) |
d94ff143 | 139 | |
a929afa6 | 140 | def putb(self, data): |
de038c47 | 141 | self.put(self.ss, self.es, self.out_binary, data) |
a929afa6 | 142 | |
592f355b | 143 | def handle_start(self, pins): |
de038c47 | 144 | self.ss, self.es = self.samplenum, self.samplenum |
8d2a9636 BV |
145 | self.pdu_start = self.samplenum |
146 | self.pdu_bits = 0 | |
14ba515b | 147 | cmd = 'START REPEAT' if self.is_repeat_start else 'START' |
d94ff143 | 148 | self.putp([cmd, None]) |
01416b98 GS |
149 | cls, texts = proto[cmd][0], proto[cmd][1:] |
150 | self.putx([cls, texts]) | |
2b716038 | 151 | self.state = 'FIND ADDRESS' |
14ba515b GS |
152 | self.is_repeat_start = True |
153 | self.is_write = None | |
4f139c28 | 154 | self.rem_addr_bytes = None |
647aba6a | 155 | self.data_bits.clear() |
7b86f0bc | 156 | |
c4975078 | 157 | # Gather 8 bits of data plus the ACK/NACK bit. |
592f355b UH |
158 | def handle_address_or_data(self, pins): |
159 | scl, sda = pins | |
160 | self.pdu_bits += 1 | |
161 | ||
647aba6a GS |
162 | # Accumulate a byte's bits, including its start position. |
163 | # Accumulate individual bits and their start/end sample numbers | |
164 | # as we see them. Get the start sample number at the time when | |
165 | # the bit value gets sampled. Assume the start of the next bit | |
166 | # as the end sample number of the previous bit. Guess the last | |
167 | # bit's end sample number from the second last bit's width. | |
168 | # (gsi: Shouldn't falling SCL be the end of the bit value?) | |
169 | # Keep the bits in receive order (MSB first) during accumulation. | |
170 | if not self.data_bits: | |
486b19ce | 171 | self.ss_byte = self.samplenum |
647aba6a GS |
172 | if self.data_bits: |
173 | self.data_bits[-1][2] = self.samplenum | |
174 | self.data_bits.append([sda, self.samplenum, self.samplenum]) | |
175 | if len(self.data_bits) < 8: | |
eb7082c9 | 176 | return |
647aba6a GS |
177 | self.bitwidth = self.data_bits[-2][2] - self.data_bits[-3][2] |
178 | self.data_bits[-1][2] += self.bitwidth | |
7b86f0bc | 179 | |
647aba6a GS |
180 | # Get the byte value. Address and data are transmitted MSB-first. |
181 | d = bitpack_msb(self.data_bits, 0) | |
2b716038 | 182 | if self.state == 'FIND ADDRESS': |
4f139c28 GS |
183 | # The READ/WRITE bit is only in the first address byte, not |
184 | # in data bytes. Address bit pattern 0b1111_0xxx means that | |
185 | # this is a 10bit slave address, another byte follows. Get | |
186 | # the R/W direction and the address bytes count from the | |
187 | # first byte in the I2C transfer. | |
188 | addr_byte = d | |
189 | if self.rem_addr_bytes is None: | |
190 | if (addr_byte & 0xf8) == 0xf0: | |
191 | self.rem_addr_bytes = 2 | |
192 | self.slave_addr_7 = None | |
193 | self.slave_addr_10 = addr_byte & 0x06 | |
194 | self.slave_addr_10 <<= 7 | |
195 | else: | |
196 | self.rem_addr_bytes = 1 | |
197 | self.slave_addr_7 = addr_byte >> 1 | |
198 | self.slave_addr_10 = None | |
199 | is_seven = self.slave_addr_7 is not None | |
200 | if self.is_write is None: | |
201 | read_bit = bool(addr_byte & 1) | |
202 | shift_seven = self.options['address_format'] == 'shifted' | |
203 | if is_seven and shift_seven: | |
204 | d = d >> 1 | |
205 | self.is_write = False if read_bit else True | |
206 | else: | |
207 | self.slave_addr_10 |= addr_byte | |
15969949 | 208 | |
a929afa6 | 209 | bin_class = -1 |
14ba515b | 210 | if self.state == 'FIND ADDRESS' and self.is_write: |
a2d2aff2 | 211 | cmd = 'ADDRESS WRITE' |
a929afa6 | 212 | bin_class = 1 |
14ba515b | 213 | elif self.state == 'FIND ADDRESS' and not self.is_write: |
a2d2aff2 | 214 | cmd = 'ADDRESS READ' |
a929afa6 | 215 | bin_class = 0 |
14ba515b | 216 | elif self.state == 'FIND DATA' and self.is_write: |
a2d2aff2 | 217 | cmd = 'DATA WRITE' |
a929afa6 | 218 | bin_class = 3 |
14ba515b | 219 | elif self.state == 'FIND DATA' and not self.is_write: |
a2d2aff2 | 220 | cmd = 'DATA READ' |
a929afa6 | 221 | bin_class = 2 |
eb7082c9 | 222 | |
486b19ce | 223 | self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth |
de038c47 | 224 | |
647aba6a GS |
225 | # Reverse the list of bits to LSB first order before emitting |
226 | # annotations and passing bits to upper layers. This may be | |
227 | # unexpected because the protocol is MSB first, but it keeps | |
228 | # backwards compatibility. | |
229 | self.data_bits.reverse() | |
14ba515b | 230 | self.putp(['BITS', self.data_bits]) |
d94ff143 | 231 | self.putp([cmd, d]) |
de038c47 | 232 | |
2824e811 | 233 | self.putb([bin_class, bytes([d])]) |
7b86f0bc | 234 | |
01416b98 GS |
235 | for b, ss, es in self.data_bits: |
236 | cls, texts = proto['BIT'][0], proto['BIT'][1:] | |
237 | texts = [t.format(b = b) for t in texts] | |
238 | self.put(ss, es, self.out_ann, [cls, texts]) | |
de038c47 | 239 | |
4f139c28 | 240 | if cmd.startswith('ADDRESS') and is_seven: |
de038c47 | 241 | self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth |
01416b98 | 242 | cls = proto[cmd][0] |
14ba515b | 243 | w = ['Write', 'Wr', 'W'] if self.is_write else ['Read', 'Rd', 'R'] |
01416b98 | 244 | self.putx([cls, w]) |
486b19ce | 245 | self.ss, self.es = self.ss_byte, self.samplenum |
de038c47 | 246 | |
01416b98 GS |
247 | cls, texts = proto[cmd][0], proto[cmd][1:] |
248 | texts = [t.format(b = d) for t in texts] | |
249 | self.putx([cls, texts]) | |
de038c47 | 250 | |
1b75abfd | 251 | # Done with this packet. |
647aba6a | 252 | self.data_bits.clear() |
2b716038 | 253 | self.state = 'FIND ACK' |
7b86f0bc | 254 | |
592f355b UH |
255 | def get_ack(self, pins): |
256 | scl, sda = pins | |
de038c47 | 257 | self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth |
d94ff143 UH |
258 | cmd = 'NACK' if (sda == 1) else 'ACK' |
259 | self.putp([cmd, None]) | |
01416b98 GS |
260 | cls, texts = proto[cmd][0], proto[cmd][1:] |
261 | self.putx([cls, texts]) | |
4f139c28 GS |
262 | # Slave addresses can span one or two bytes, before data bytes |
263 | # follow. There can be an arbitrary number of data bytes. Stick | |
264 | # with getting more address bytes if applicable, or enter or | |
265 | # remain in the data phase of the transfer otherwise. | |
266 | if self.rem_addr_bytes: | |
267 | self.rem_addr_bytes -= 1 | |
268 | if self.rem_addr_bytes: | |
269 | self.state = 'FIND ADDRESS' | |
270 | else: | |
271 | self.state = 'FIND DATA' | |
7b86f0bc | 272 | |
592f355b | 273 | def handle_stop(self, pins): |
8d2a9636 | 274 | # Meta bitrate |
8accc30b GS |
275 | if self.samplerate: |
276 | elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1) | |
277 | bitrate = int(1 / elapsed * self.pdu_bits) | |
278 | self.put(self.ss_byte, self.samplenum, self.out_bitrate, bitrate) | |
8d2a9636 | 279 | |
d94ff143 | 280 | cmd = 'STOP' |
de038c47 | 281 | self.ss, self.es = self.samplenum, self.samplenum |
d94ff143 | 282 | self.putp([cmd, None]) |
01416b98 GS |
283 | cls, texts = proto[cmd][0], proto[cmd][1:] |
284 | self.putx([cls, texts]) | |
2b716038 | 285 | self.state = 'FIND START' |
14ba515b GS |
286 | self.is_repeat_start = False |
287 | self.is_write = None | |
647aba6a | 288 | self.data_bits.clear() |
7b86f0bc | 289 | |
592f355b | 290 | def decode(self): |
592f355b | 291 | while True: |
7b86f0bc | 292 | # State machine. |
2b716038 | 293 | if self.state == 'FIND START': |
592f355b UH |
294 | # Wait for a START condition (S): SCL = high, SDA = falling. |
295 | self.handle_start(self.wait({0: 'h', 1: 'f'})) | |
2b716038 | 296 | elif self.state == 'FIND ADDRESS': |
592f355b UH |
297 | # Wait for a data bit: SCL = rising. |
298 | self.handle_address_or_data(self.wait({0: 'r'})) | |
2b716038 | 299 | elif self.state == 'FIND DATA': |
592f355b UH |
300 | # Wait for any of the following conditions (or combinations): |
301 | # a) Data sampling of receiver: SCL = rising, and/or | |
302 | # b) START condition (S): SCL = high, SDA = falling, and/or | |
303 | # c) STOP condition (P): SCL = high, SDA = rising | |
fcd5d23a | 304 | pins = self.wait([{0: 'r'}, {0: 'h', 1: 'f'}, {0: 'h', 1: 'r'}]) |
592f355b UH |
305 | |
306 | # Check which of the condition(s) matched and handle them. | |
307 | if self.matched[0]: | |
308 | self.handle_address_or_data(pins) | |
309 | elif self.matched[1]: | |
310 | self.handle_start(pins) | |
311 | elif self.matched[2]: | |
312 | self.handle_stop(pins) | |
2b716038 | 313 | elif self.state == 'FIND ACK': |
592f355b UH |
314 | # Wait for a data/ack bit: SCL = rising. |
315 | self.get_ack(self.wait({0: 'r'})) |