]>
Commit | Line | Data |
---|---|---|
0588ed70 UH |
1 | ## |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
7b86f0bc | 4 | ## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de> |
0588ed70 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
0588ed70 | 21 | # I2C protocol decoder |
0588ed70 UH |
22 | |
23 | # TODO: Look into arbitration, collision detection, clock synchronisation, etc. | |
24 | # TODO: Handle clock stretching. | |
25 | # TODO: Handle combined messages / repeated START. | |
26 | # TODO: Implement support for 7bit and 10bit slave addresses. | |
27 | # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). | |
28 | # TODO: Implement support for detecting various bus errors. | |
23fb2e12 UH |
29 | # TODO: I2C address of slaves. |
30 | # TODO: Handle multiple different I2C devices on same bus | |
31 | # -> we need to decode multiple protocols at the same time. | |
23fb2e12 | 32 | |
677d597b | 33 | import sigrokdecode as srd |
b2c19614 | 34 | |
eb7082c9 | 35 | # Annotation feed formats |
7ce7775c BV |
36 | ANN_SHIFTED = 0 |
37 | ANN_SHIFTED_SHORT = 1 | |
38 | ANN_RAW = 2 | |
39 | ||
eb7082c9 | 40 | # Values are verbose and short annotation, respectively. |
15969949 | 41 | protocol = { |
eb7082c9 | 42 | 'START': ['START', 'S'], |
a2d2aff2 | 43 | 'START REPEAT': ['START REPEAT', 'Sr'], |
eb7082c9 UH |
44 | 'STOP': ['STOP', 'P'], |
45 | 'ACK': ['ACK', 'A'], | |
46 | 'NACK': ['NACK', 'N'], | |
a2d2aff2 UH |
47 | 'ADDRESS READ': ['ADDRESS READ', 'AR'], |
48 | 'ADDRESS WRITE': ['ADDRESS WRITE', 'AW'], | |
49 | 'DATA READ': ['DATA READ', 'DR'], | |
50 | 'DATA WRITE': ['DATA WRITE', 'DW'], | |
15969949 | 51 | } |
e5080882 | 52 | |
400f9ae7 UH |
53 | # States |
54 | FIND_START = 0 | |
55 | FIND_ADDRESS = 1 | |
56 | FIND_DATA = 2 | |
57 | ||
677d597b | 58 | class Decoder(srd.Decoder): |
a2c2afd9 | 59 | api_version = 1 |
67e847fd | 60 | id = 'i2c' |
f39d2404 | 61 | name = 'I2C' |
9a12a6e7 | 62 | longname = 'Inter-Integrated Circuit' |
f39d2404 UH |
63 | desc = 'I2C is a two-wire, multi-master, serial bus.' |
64 | longdesc = '...' | |
f39d2404 UH |
65 | license = 'gplv2+' |
66 | inputs = ['logic'] | |
67 | outputs = ['i2c'] | |
bc5f5a43 BV |
68 | probes = [ |
69 | {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'}, | |
70 | {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, | |
71 | ] | |
b77614bc | 72 | optional_probes = [] |
f39d2404 | 73 | options = { |
ea90233e | 74 | 'addressing': ['Slave addressing (in bits)', 7], # 7 or 10 |
ad2dc0de | 75 | } |
e97b6ef5 | 76 | annotations = [ |
15969949 | 77 | # ANN_SHIFTED |
eb7082c9 UH |
78 | ['7-bit shifted hex', |
79 | 'Read/write bit shifted out from the 8-bit I2C slave address'], | |
15969949 | 80 | # ANN_SHIFTED_SHORT |
eb7082c9 UH |
81 | ['7-bit shifted hex (short)', |
82 | 'Read/write bit shifted out from the 8-bit I2C slave address'], | |
15969949 | 83 | # ANN_RAW |
eb7082c9 | 84 | ['Raw hex', 'Unaltered raw data'], |
15969949 | 85 | ] |
0588ed70 | 86 | |
3643fc3f | 87 | def __init__(self, **kwargs): |
c4975078 BV |
88 | self.startsample = -1 |
89 | self.samplenum = None | |
f39d2404 UH |
90 | self.bitcount = 0 |
91 | self.databyte = 0 | |
92 | self.wr = -1 | |
5dd9af5b | 93 | self.is_repeat_start = 0 |
400f9ae7 | 94 | self.state = FIND_START |
f39d2404 UH |
95 | self.oldscl = None |
96 | self.oldsda = None | |
97 | ||
3643fc3f | 98 | def start(self, metadata): |
56202222 UH |
99 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c') |
100 | self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c') | |
3643fc3f | 101 | |
decde15e UH |
102 | def report(self): |
103 | pass | |
104 | ||
7b86f0bc | 105 | def is_start_condition(self, scl, sda): |
eb7082c9 | 106 | # START condition (S): SDA = falling, SCL = high |
7b86f0bc UH |
107 | if (self.oldsda == 1 and sda == 0) and scl == 1: |
108 | return True | |
109 | return False | |
110 | ||
111 | def is_data_bit(self, scl, sda): | |
eb7082c9 | 112 | # Data sampling of receiver: SCL = rising |
7b86f0bc UH |
113 | if self.oldscl == 0 and scl == 1: |
114 | return True | |
115 | return False | |
116 | ||
117 | def is_stop_condition(self, scl, sda): | |
eb7082c9 | 118 | # STOP condition (P): SDA = rising, SCL = high |
7b86f0bc UH |
119 | if (self.oldsda == 0 and sda == 1) and scl == 1: |
120 | return True | |
121 | return False | |
122 | ||
e5080882 | 123 | def found_start(self, scl, sda): |
c4975078 | 124 | self.startsample = self.samplenum |
eb7082c9 | 125 | |
c4975078 | 126 | cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START' |
eb7082c9 UH |
127 | self.put(self.out_proto, [cmd, None, None]) |
128 | self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]]) | |
129 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]]) | |
e5080882 | 130 | |
400f9ae7 | 131 | self.state = FIND_ADDRESS |
7b86f0bc | 132 | self.bitcount = self.databyte = 0 |
5dd9af5b | 133 | self.is_repeat_start = 1 |
7b86f0bc | 134 | self.wr = -1 |
7b86f0bc | 135 | |
c4975078 | 136 | # Gather 8 bits of data plus the ACK/NACK bit. |
e5080882 | 137 | def found_address_or_data(self, scl, sda): |
7b86f0bc UH |
138 | # Address and data are transmitted MSB-first. |
139 | self.databyte <<= 1 | |
140 | self.databyte |= sda | |
141 | ||
c4975078 BV |
142 | if self.bitcount == 0: |
143 | self.startsample = self.samplenum | |
144 | ||
7b86f0bc | 145 | # Return if we haven't collected all 8 + 1 bits, yet. |
c4975078 | 146 | self.bitcount += 1 |
7b86f0bc | 147 | if self.bitcount != 9: |
eb7082c9 | 148 | return |
7b86f0bc | 149 | |
eb7082c9 UH |
150 | # Send raw output annotation before we start shifting out |
151 | # read/write and ack/nack bits. | |
152 | self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]]) | |
15969949 | 153 | |
7b86f0bc UH |
154 | # We received 8 address/data bits and the ACK/NACK bit. |
155 | self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here. | |
156 | ||
400f9ae7 | 157 | if self.state == FIND_ADDRESS: |
7b86f0bc | 158 | # The READ/WRITE bit is only in address bytes, not data bytes. |
bf1c3f4d | 159 | self.wr = 0 if (self.databyte & 1) else 1 |
84b81f1d | 160 | d = self.databyte >> 1 |
400f9ae7 | 161 | elif self.state == FIND_DATA: |
7b86f0bc UH |
162 | d = self.databyte |
163 | else: | |
164 | # TODO: Error? | |
165 | pass | |
166 | ||
eb7082c9 | 167 | # Last bit that came in was the ACK/NACK bit (1 = NACK). |
bf1c3f4d | 168 | ack_bit = 'NACK' if (sda == 1) else 'ACK' |
15969949 | 169 | |
400f9ae7 | 170 | if self.state == FIND_ADDRESS and self.wr == 1: |
a2d2aff2 | 171 | cmd = 'ADDRESS WRITE' |
400f9ae7 | 172 | elif self.state == FIND_ADDRESS and self.wr == 0: |
a2d2aff2 | 173 | cmd = 'ADDRESS READ' |
400f9ae7 | 174 | elif self.state == FIND_DATA and self.wr == 1: |
a2d2aff2 | 175 | cmd = 'DATA WRITE' |
400f9ae7 | 176 | elif self.state == FIND_DATA and self.wr == 0: |
a2d2aff2 | 177 | cmd = 'DATA READ' |
eb7082c9 UH |
178 | |
179 | self.put(self.out_proto, [cmd, d, ack_bit]) | |
957da073 UH |
180 | self.put(self.out_ann, [ANN_SHIFTED, |
181 | [protocol[cmd][0], '0x%02x' % d, protocol[ack_bit][0]]]) | |
182 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, | |
183 | [protocol[cmd][1], '0x%02x' % d, protocol[ack_bit][1]]]) | |
7b86f0bc | 184 | |
7b86f0bc UH |
185 | self.bitcount = self.databyte = 0 |
186 | self.startsample = -1 | |
187 | ||
400f9ae7 UH |
188 | if self.state == FIND_ADDRESS: |
189 | self.state = FIND_DATA | |
190 | elif self.state == FIND_DATA: | |
7b86f0bc UH |
191 | # There could be multiple data bytes in a row. |
192 | # So, either find a STOP condition or another data byte next. | |
193 | pass | |
194 | ||
e5080882 | 195 | def found_stop(self, scl, sda): |
c4975078 BV |
196 | self.startsample = self.samplenum |
197 | ||
eb7082c9 UH |
198 | self.put(self.out_proto, ['STOP', None, None]) |
199 | self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]]) | |
200 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]]) | |
7b86f0bc | 201 | |
400f9ae7 | 202 | self.state = FIND_START |
5dd9af5b | 203 | self.is_repeat_start = 0 |
7b86f0bc UH |
204 | self.wr = -1 |
205 | ||
1aef2f93 | 206 | def put(self, output_id, data): |
eb7082c9 | 207 | # Inject sample range into the call up to sigrok. |
c4975078 | 208 | super(Decoder, self).put(self.startsample, self.samplenum, output_id, data) |
1aef2f93 | 209 | |
2b9837d9 | 210 | def decode(self, ss, es, data): |
bc5f5a43 | 211 | for samplenum, (scl, sda) in data: |
c4975078 | 212 | self.samplenum = samplenum |
f39d2404 UH |
213 | |
214 | # First sample: Save SCL/SDA value. | |
215 | if self.oldscl == None: | |
bc5f5a43 BV |
216 | self.oldscl = scl |
217 | self.oldsda = sda | |
ad2dc0de | 218 | continue |
0588ed70 | 219 | |
f39d2404 UH |
220 | # TODO: Wait until the bus is idle (SDA = SCL = 1) first? |
221 | ||
7b86f0bc | 222 | # State machine. |
400f9ae7 | 223 | if self.state == FIND_START: |
7b86f0bc | 224 | if self.is_start_condition(scl, sda): |
e5080882 | 225 | self.found_start(scl, sda) |
400f9ae7 | 226 | elif self.state == FIND_ADDRESS: |
7b86f0bc | 227 | if self.is_data_bit(scl, sda): |
e5080882 | 228 | self.found_address_or_data(scl, sda) |
400f9ae7 | 229 | elif self.state == FIND_DATA: |
7b86f0bc | 230 | if self.is_data_bit(scl, sda): |
e5080882 | 231 | self.found_address_or_data(scl, sda) |
7b86f0bc | 232 | elif self.is_start_condition(scl, sda): |
e5080882 | 233 | self.found_start(scl, sda) |
7b86f0bc | 234 | elif self.is_stop_condition(scl, sda): |
e5080882 | 235 | self.found_stop(scl, sda) |
7b86f0bc | 236 | else: |
decde15e | 237 | raise Exception('Invalid state %d' % self.STATE) |
f39d2404 UH |
238 | |
239 | # Save current SDA/SCL values for the next round. | |
240 | self.oldscl = scl | |
241 | self.oldsda = sda | |
242 |