[libsigrokdecode.git] / decoders / em4100 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2015 Benjamin Larsson <benjamin@southpole.se>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either data 2 of the License, or
## (at your option) any later data.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

class SamplerateError(Exception):
    pass

class Decoder(srd.Decoder):
    api_version = 2
    id = 'em4100'
    name = 'EM4100'
    longname = 'RFID EM4100'
    desc = 'EM4100 100-150kHz RFID protocol.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['em4100']
    channels = (
        {'id': 'data', 'name': 'Data', 'desc': 'Data line'},
    )
    options = (
        {'id': 'polarity', 'desc': 'Polarity', 'default': 'active-high',
            'values': ('active-low', 'active-high')},
        {'id': 'datarate' , 'desc': 'Data rate', 'default': 64,
            'values': (64, 32, 16)},
#        {'id': 'coding', 'desc': 'Bit coding', 'default': 'biphase',
#            'values': ('biphase', 'manchester', 'psk')},
        {'id': 'coilfreq', 'desc': 'Coil frequency', 'default': 125000},
    )
    annotations = (
        ('bit', 'Bit'),
        ('header', 'Header'),
        ('version-customer', 'Version/customer'),
        ('data', 'Data'),
        ('rowparity-ok', 'Row parity OK'),
        ('rowparity-err', 'Row parity error'),
        ('colparity-ok', 'Column parity OK'),
        ('colparity-err', 'Column parity error'),
        ('stopbit', 'Stop bit'),
        ('tag', 'Tag'),
    )
    annotation_rows = (
        ('bits', 'Bits', (0,)),
        ('fields', 'Fields', (1, 2, 3, 4, 5, 6, 7, 8)),
        ('tags', 'Tags', (9,)),
    )

    def __init__(self, **kwargs):
        self.samplerate = None
        self.oldpin = None
        self.last_samplenum = None
        self.lastlast_samplenum = None
        self.last_edge = 0
        self.bit_width = 0
        self.halfbit_limit = 0
        self.oldpp = 0
        self.oldpl = 0
        self.oldsamplenum = 0
        self.last_bit_pos = 0
        self.first_ss = 0
        self.first_one = 0
        self.state = 'HEADER'
        self.data = 0
        self.data_bits = 0
        self.data_ss = 0
        self.data_parity = 0
        self.payload_cnt = 0
        self.data_col_parity = [0, 0, 0, 0, 0, 0]
        self.col_parity = [0, 0, 0, 0, 0, 0]
        self.tag = 0
        self.all_row_parity_ok = True
        self.col_parity_pos = []

    def metadata(self, key, value):
        if key == srd.SRD_CONF_SAMPLERATE:
            self.samplerate = value
        self.bit_width = (self.samplerate / self.options['coilfreq']) * self.options['datarate']
        self.halfbit_limit = self.bit_width/2 + self.bit_width/4
        self.polarity = 0 if self.options['polarity'] == 'active-low' else 1

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def add_bit(self, bit, ss, es):
        if self.state == 'HEADER':
            if bit == 1:
                if self.first_one > 0:
                    self.first_one += 1
                if self.first_one == 9:
                    self.put(self.first_ss, es, self.out_ann,
                             [1, ['Header', 'Head', 'He', 'H']])
                    self.first_one = 0
                    self.state = 'PAYLOAD'
                    return
                if self.first_one == 0:
                    self.first_one = 1
                    self.first_ss = ss

            if bit == 0:
                self.first_one = 0
            return

        if self.state == 'PAYLOAD':
            self.payload_cnt += 1
            if self.data_bits == 0:
                self.data_ss = ss
                self.data = 0
                self.data_parity = 0
            self.data_bits += 1
            if self.data_bits == 5:
                s = 'Version/customer' if self.payload_cnt <= 10 else 'Data'
                c = 2 if self.payload_cnt <= 10 else 3
                self.put(self.data_ss, ss, self.out_ann,
                         [c, [s + ': %X' % self.data, '%X' % self.data]])
                s = 'OK' if self.data_parity == bit else 'ERROR'
                c = 4 if s == 'OK' else 5
                if s == 'ERROR':
                    self.all_row_parity_ok = False
                self.put(ss, es, self.out_ann,
                         [c, ['Row parity: ' + s, 'RP: ' + s, 'RP', 'R']])
                self.tag = (self.tag << 4) | self.data
                self.data_bits = 0
                if self.payload_cnt == 50:
                    self.state = 'TRAILER'
                    self.payload_cnt = 0

            self.data_parity ^= bit
            self.data_col_parity[self.data_bits] ^= bit
            self.data = (self.data << 1) | bit
            return

        if self.state == 'TRAILER':
            self.payload_cnt += 1
            if self.data_bits == 0:
                self.data_ss = ss
                self.data = 0
                self.data_parity = 0
            self.data_bits += 1
            self.col_parity[self.data_bits] = bit
            self.col_parity_pos.append([ss, es])

            if self.data_bits == 5:
                self.put(ss, es, self.out_ann, [8, ['Stop bit', 'SB', 'S']])

                for i in range(1, 5):
                    s = 'OK' if self.data_col_parity[i] == \
                                self.col_parity[i] else 'ERROR'
                    c = 6 if s == 'OK' else 7
                    self.put(self.col_parity_pos[i - 1][0],
                             self.col_parity_pos[i - 1][1], self.out_ann,
                             [c, ['Column parity %d: %s' % (i, s),
                                  'CP%d: %s' % (i, s), 'CP%d' % i, 'C']])

                # Emit an annotation for valid-looking tags.
                all_col_parity_ok = (self.data_col_parity[1:5] == self.col_parity[1:5])
                if all_col_parity_ok and self.all_row_parity_ok:
                    self.put(self.first_ss, es, self.out_ann,
                             [9, ['Tag: %010X' % self.tag, 'Tag', 'T']])

                self.tag = 0
                self.data_bits = 0

                if self.payload_cnt == 5:
                    self.state = 'HEADER'
                    self.payload_cnt = 0
                    self.data_col_parity = [0, 0, 0, 0, 0, 0]
                    self.col_parity = [0, 0, 0, 0, 0, 0]
                    self.col_parity_pos = []
                    self.all_row_parity_ok = True

    def putbit(self, bit, ss, es):
        self.put(ss, es, self.out_ann, [0, [str(bit)]])
        self.add_bit(bit, ss, es)

    def manchester_decode(self, samplenum, pl, pp, pin):
        ss, es = 0, 0
        bit = self.oldpin ^ self.polarity
        if pl > self.halfbit_limit:
            samples = samplenum - self.oldsamplenum
            t = samples / self.samplerate

            if self.oldpl > self.halfbit_limit:
                ss = int(self.oldsamplenum - self.oldpl/2)
                es = int(samplenum - pl/2)
                self.putbit(bit, ss, es)
            if self.oldpl <= self.halfbit_limit:
                ss = int(self.oldsamplenum - self.oldpl)
                es = int(samplenum - pl/2)
                self.putbit(bit, ss, es)
            self.last_bit_pos = int(samplenum - pl/2)

        if pl < self.halfbit_limit:
            samples = samplenum - self.oldsamplenum
            t = samples / self.samplerate

            if self.oldpl > self.halfbit_limit:
                ss = int(self.oldsamplenum - self.oldpl/2)
                es = int(samplenum)
                self.putbit(bit, ss, es)
                self.last_bit_pos = int(samplenum)
            if self.oldpl <= self.halfbit_limit:
                if self.last_bit_pos <= self.oldsamplenum - self.oldpl:
                    ss = int(self.oldsamplenum - self.oldpl)
                    es = int(samplenum)
                    self.putbit(bit, ss, es)
                    self.last_bit_pos = int(samplenum)

    def decode(self, ss, es, data):
        if not self.samplerate:
            raise SamplerateError('Cannot decode without samplerate.')
        for (samplenum, (pin,)) in data:
            # Ignore identical samples early on (for performance reasons).
            if self.oldpin == pin:
                continue

            if self.oldpin is None:
                self.oldpin = pin
                self.last_samplenum = samplenum
                self.lastlast_samplenum = samplenum
                self.last_edge = samplenum
                self.oldpl = 0
                self.oldpp = 0
                self.oldsamplenum = 0
                self.last_bit_pos = 0
                continue

            if self.oldpin != pin:
                pl = samplenum - self.oldsamplenum
                pp = pin

                self.manchester_decode(samplenum, pl, pp, pin)

                self.oldpl = pl
                self.oldpp = pp
                self.oldsamplenum = samplenum
                self.oldpin = pin
Commit	Line	Data
8f265907 BL	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2015 Benjamin Larsson <benjamin@southpole.se>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either data 2 of the License, or
	9	## (at your option) any later data.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	import sigrokdecode as srd
	22
	23	class SamplerateError(Exception):
	24	pass
	25
	26	class Decoder(srd.Decoder):
	27	api_version = 2
	28	id = 'em4100'
	29	name = 'EM4100'
	30	longname = 'RFID EM4100'
	31	desc = 'EM4100 100-150kHz RFID protocol.'
	32	license = 'gplv2+'
	33	inputs = ['logic']
	34	outputs = ['em4100']
	35	channels = (
	36	{'id': 'data', 'name': 'Data', 'desc': 'Data line'},
	37	)
	38	options = (
	39	{'id': 'polarity', 'desc': 'Polarity', 'default': 'active-high',
	40	'values': ('active-low', 'active-high')},
1a782fad UH	41	{'id': 'datarate' , 'desc': 'Data rate', 'default': 64,
1a782fad UH	42	'values': (64, 32, 16)},
8f265907 BL	43	# {'id': 'coding', 'desc': 'Bit coding', 'default': 'biphase',
8f265907 BL	44	# 'values': ('biphase', 'manchester', 'psk')},
1a782fad	45	{'id': 'coilfreq', 'desc': 'Coil frequency', 'default': 125000},
8f265907 BL	46	)
8f265907 BL	47	annotations = (
428e40cb UH	48	('bit', 'Bit'),
	49	('header', 'Header'),
	50	('version-customer', 'Version/customer'),
	51	('data', 'Data'),
	52	('rowparity-ok', 'Row parity OK'),
	53	('rowparity-err', 'Row parity error'),
	54	('colparity-ok', 'Column parity OK'),
	55	('colparity-err', 'Column parity error'),
8f265907	56	('stopbit', 'Stop bit'),
428e40cb	57	('tag', 'Tag'),
8f265907 BL	58	)
	59	annotation_rows = (
	60	('bits', 'Bits', (0,)),
428e40cb UH	61	('fields', 'Fields', (1, 2, 3, 4, 5, 6, 7, 8)),
428e40cb UH	62	('tags', 'Tags', (9,)),
8f265907 BL	63	)
	64
	65	def __init__(self, **kwargs):
	66	self.samplerate = None
	67	self.oldpin = None
	68	self.last_samplenum = None
	69	self.lastlast_samplenum = None
	70	self.last_edge = 0
	71	self.bit_width = 0
	72	self.halfbit_limit = 0
	73	self.oldpp = 0
	74	self.oldpl = 0
	75	self.oldsamplenum = 0
	76	self.last_bit_pos = 0
13090f24	77	self.first_ss = 0
8f265907 BL	78	self.first_one = 0
	79	self.state = 'HEADER'
	80	self.data = 0
	81	self.data_bits = 0
13090f24	82	self.data_ss = 0
8f265907 BL	83	self.data_parity = 0
	84	self.payload_cnt = 0
	85	self.data_col_parity = [0, 0, 0, 0, 0, 0]
	86	self.col_parity = [0, 0, 0, 0, 0, 0]
428e40cb UH	87	self.tag = 0
	88	self.all_row_parity_ok = True
	89	self.col_parity_pos = []
8f265907 BL	90
	91	def metadata(self, key, value):
	92	if key == srd.SRD_CONF_SAMPLERATE:
	93	self.samplerate = value
1a782fad	94	self.bit_width = (self.samplerate / self.options['coilfreq']) * self.options['datarate']
8f265907 BL	95	self.halfbit_limit = self.bit_width/2 + self.bit_width/4
	96	self.polarity = 0 if self.options['polarity'] == 'active-low' else 1
	97
	98	def start(self):
	99	self.out_ann = self.register(srd.OUTPUT_ANN)
	100
13090f24	101	def add_bit(self, bit, ss, es):
8f265907 BL	102	if self.state == 'HEADER':
	103	if bit == 1:
	104	if self.first_one > 0:
	105	self.first_one += 1
	106	if self.first_one == 9:
13090f24	107	self.put(self.first_ss, es, self.out_ann,
8f265907 BL	108	[1, ['Header', 'Head', 'He', 'H']])
	109	self.first_one = 0
	110	self.state = 'PAYLOAD'
	111	return
	112	if self.first_one == 0:
	113	self.first_one = 1
13090f24	114	self.first_ss = ss
8f265907 BL	115
	116	if bit == 0:
	117	self.first_one = 0
	118	return
	119
	120	if self.state == 'PAYLOAD':
	121	self.payload_cnt += 1
	122	if self.data_bits == 0:
13090f24	123	self.data_ss = ss
8f265907 BL	124	self.data = 0
	125	self.data_parity = 0
	126	self.data_bits += 1
	127	if self.data_bits == 5:
428e40cb UH	128	s = 'Version/customer' if self.payload_cnt <= 10 else 'Data'
428e40cb UH	129	c = 2 if self.payload_cnt <= 10 else 3
13090f24	130	self.put(self.data_ss, ss, self.out_ann,
428e40cb UH	131	[c, [s + ': %X' % self.data, '%X' % self.data]])
	132	s = 'OK' if self.data_parity == bit else 'ERROR'
	133	c = 4 if s == 'OK' else 5
	134	if s == 'ERROR':
	135	self.all_row_parity_ok = False
13090f24	136	self.put(ss, es, self.out_ann,
428e40cb UH	137	[c, ['Row parity: ' + s, 'RP: ' + s, 'RP', 'R']])
428e40cb UH	138	self.tag = (self.tag << 4) \| self.data
8f265907 BL	139	self.data_bits = 0
	140	if self.payload_cnt == 50:
	141	self.state = 'TRAILER'
	142	self.payload_cnt = 0
	143
	144	self.data_parity ^= bit
	145	self.data_col_parity[self.data_bits] ^= bit
	146	self.data = (self.data << 1) \| bit
	147	return
	148
	149	if self.state == 'TRAILER':
	150	self.payload_cnt += 1
	151	if self.data_bits == 0:
13090f24	152	self.data_ss = ss
8f265907 BL	153	self.data = 0
	154	self.data_parity = 0
	155	self.data_bits += 1
	156	self.col_parity[self.data_bits] = bit
13090f24	157	self.col_parity_pos.append([ss, es])
8f265907 BL	158
8f265907 BL	159	if self.data_bits == 5:
13090f24	160	self.put(ss, es, self.out_ann, [8, ['Stop bit', 'SB', 'S']])
428e40cb UH	161
	162	for i in range(1, 5):
	163	s = 'OK' if self.data_col_parity[i] == \
	164	self.col_parity[i] else 'ERROR'
	165	c = 6 if s == 'OK' else 7
	166	self.put(self.col_parity_pos[i - 1][0],
	167	self.col_parity_pos[i - 1][1], self.out_ann,
	168	[c, ['Column parity %d: %s' % (i, s),
	169	'CP%d: %s' % (i, s), 'CP%d' % i, 'C']])
	170
	171	# Emit an annotation for valid-looking tags.
	172	all_col_parity_ok = (self.data_col_parity[1:5] == self.col_parity[1:5])
	173	if all_col_parity_ok and self.all_row_parity_ok:
13090f24	174	self.put(self.first_ss, es, self.out_ann,
428e40cb	175	[9, ['Tag: %010X' % self.tag, 'Tag', 'T']])
8f265907	176
428e40cb	177	self.tag = 0
8f265907	178	self.data_bits = 0
428e40cb	179
8f265907 BL	180	if self.payload_cnt == 5:
	181	self.state = 'HEADER'
	182	self.payload_cnt = 0
	183	self.data_col_parity = [0, 0, 0, 0, 0, 0]
	184	self.col_parity = [0, 0, 0, 0, 0, 0]
428e40cb UH	185	self.col_parity_pos = []
428e40cb UH	186	self.all_row_parity_ok = True
8f265907	187
13090f24 UH	188	def putbit(self, bit, ss, es):
	189	self.put(ss, es, self.out_ann, [0, [str(bit)]])
	190	self.add_bit(bit, ss, es)
8f265907 BL	191
8f265907 BL	192	def manchester_decode(self, samplenum, pl, pp, pin):
13090f24	193	ss, es = 0, 0
8f265907 BL	194	bit = self.oldpin ^ self.polarity
	195	if pl > self.halfbit_limit:
	196	samples = samplenum - self.oldsamplenum
	197	t = samples / self.samplerate
	198
	199	if self.oldpl > self.halfbit_limit:
13090f24 UH	200	ss = int(self.oldsamplenum - self.oldpl/2)
	201	es = int(samplenum - pl/2)
	202	self.putbit(bit, ss, es)
8f265907	203	if self.oldpl <= self.halfbit_limit:
13090f24 UH	204	ss = int(self.oldsamplenum - self.oldpl)
	205	es = int(samplenum - pl/2)
	206	self.putbit(bit, ss, es)
8f265907 BL	207	self.last_bit_pos = int(samplenum - pl/2)
	208
	209	if pl < self.halfbit_limit:
	210	samples = samplenum - self.oldsamplenum
	211	t = samples / self.samplerate
	212
	213	if self.oldpl > self.halfbit_limit:
13090f24 UH	214	ss = int(self.oldsamplenum - self.oldpl/2)
	215	es = int(samplenum)
	216	self.putbit(bit, ss, es)
8f265907 BL	217	self.last_bit_pos = int(samplenum)
	218	if self.oldpl <= self.halfbit_limit:
	219	if self.last_bit_pos <= self.oldsamplenum - self.oldpl:
13090f24 UH	220	ss = int(self.oldsamplenum - self.oldpl)
	221	es = int(samplenum)
	222	self.putbit(bit, ss, es)
8f265907 BL	223	self.last_bit_pos = int(samplenum)
	224
	225	def decode(self, ss, es, data):
	226	if not self.samplerate:
	227	raise SamplerateError('Cannot decode without samplerate.')
	228	for (samplenum, (pin,)) in data:
	229	# Ignore identical samples early on (for performance reasons).
	230	if self.oldpin == pin:
	231	continue
	232
	233	if self.oldpin is None:
	234	self.oldpin = pin
	235	self.last_samplenum = samplenum
	236	self.lastlast_samplenum = samplenum
	237	self.last_edge = samplenum
	238	self.oldpl = 0
	239	self.oldpp = 0
	240	self.oldsamplenum = 0
	241	self.last_bit_pos = 0
	242	continue
	243
	244	if self.oldpin != pin:
	245	pl = samplenum - self.oldsamplenum
	246	pp = pin
	247
	248	self.manchester_decode(samplenum, pl, pp, pin)
	249
	250	self.oldpl = pl
	251	self.oldpp = pp
	252	self.oldsamplenum = samplenum
	253	self.oldpin = pin