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Commit | Line | Data |
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702fa251 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
702fa251 | 3 | ## |
e20f455c | 4 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
38b40330 | 5 | ## Copyright (C) 2019 Stephan Thiele <stephan.thiele@mailbox.org> |
702fa251 UH |
6 | ## |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 18 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
702fa251 | 19 | ## |
702fa251 | 20 | |
b0edaeb3 | 21 | from common.srdhelper import bitpack |
702fa251 UH |
22 | import sigrokdecode as srd |
23 | ||
21cda951 UH |
24 | class SamplerateError(Exception): |
25 | pass | |
26 | ||
ad373029 UH |
27 | def dlc2len(dlc): |
28 | return [0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64][dlc] | |
29 | ||
702fa251 | 30 | class Decoder(srd.Decoder): |
64d87119 | 31 | api_version = 3 |
702fa251 UH |
32 | id = 'can' |
33 | name = 'CAN' | |
9e1437a0 | 34 | longname = 'Controller Area Network' |
702fa251 UH |
35 | desc = 'Field bus protocol for distributed realtime control.' |
36 | license = 'gplv2+' | |
37 | inputs = ['logic'] | |
7ecd283c | 38 | outputs = ['can'] |
d6d8a8a4 | 39 | tags = ['Automotive'] |
6a15597a | 40 | channels = ( |
702fa251 | 41 | {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'}, |
da9bcbd9 | 42 | ) |
84c1c0b5 | 43 | options = ( |
3b593817 UH |
44 | {'id': 'nominal_bitrate', 'desc': 'Nominal bitrate (bits/s)', 'default': 1000000}, |
45 | {'id': 'fast_bitrate', 'desc': 'Fast bitrate (bits/s)', 'default': 2000000}, | |
b0918d40 | 46 | {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0}, |
84c1c0b5 | 47 | ) |
da9bcbd9 | 48 | annotations = ( |
e144452b | 49 | ('data', 'Payload data'), |
da9bcbd9 BV |
50 | ('sof', 'Start of frame'), |
51 | ('eof', 'End of frame'), | |
52 | ('id', 'Identifier'), | |
53 | ('ext-id', 'Extended identifier'), | |
54 | ('full-id', 'Full identifier'), | |
55 | ('ide', 'Identifier extension bit'), | |
56 | ('reserved-bit', 'Reserved bit 0 and 1'), | |
57 | ('rtr', 'Remote transmission request'), | |
58 | ('srr', 'Substitute remote request'), | |
59 | ('dlc', 'Data length count'), | |
60 | ('crc-sequence', 'CRC sequence'), | |
61 | ('crc-delimiter', 'CRC delimiter'), | |
62 | ('ack-slot', 'ACK slot'), | |
63 | ('ack-delimiter', 'ACK delimiter'), | |
64 | ('stuff-bit', 'Stuff bit'), | |
e144452b | 65 | ('warning', 'Warning'), |
544038d9 | 66 | ('bit', 'Bit'), |
d4a28d0f UH |
67 | ) |
68 | annotation_rows = ( | |
544038d9 | 69 | ('bits', 'Bits', (15, 17)), |
2fac4493 UH |
70 | ('fields', 'Fields', tuple(range(15))), |
71 | ('warnings', 'Warnings', (16,)), | |
da9bcbd9 | 72 | ) |
702fa251 | 73 | |
92b7b49f | 74 | def __init__(self): |
10aeb8ea GS |
75 | self.reset() |
76 | ||
77 | def reset(self): | |
f372d597 | 78 | self.samplerate = None |
702fa251 UH |
79 | self.reset_variables() |
80 | ||
f372d597 | 81 | def start(self): |
be465111 | 82 | self.out_ann = self.register(srd.OUTPUT_ANN) |
7ecd283c | 83 | self.out_python = self.register(srd.OUTPUT_PYTHON) |
702fa251 | 84 | |
8abd7aa3 ST |
85 | def set_bit_rate(self, bitrate): |
86 | self.bit_width = float(self.samplerate) / float(bitrate) | |
87 | self.sample_point = (self.bit_width / 100.0) * self.options['sample_point'] | |
88 | ||
89 | def set_nominal_bitrate(self): | |
90 | self.set_bit_rate(self.options['nominal_bitrate']) | |
91 | ||
92 | def set_fast_bitrate(self): | |
93 | self.set_bit_rate(self.options['fast_bitrate']) | |
94 | ||
f372d597 BV |
95 | def metadata(self, key, value): |
96 | if key == srd.SRD_CONF_SAMPLERATE: | |
97 | self.samplerate = value | |
2d9e1115 | 98 | self.bit_width = float(self.samplerate) / float(self.options['nominal_bitrate']) |
300f9194 | 99 | self.sample_point = (self.bit_width / 100.0) * self.options['sample_point'] |
702fa251 | 100 | |
4b1813b4 UH |
101 | # Generic helper for CAN bit annotations. |
102 | def putg(self, ss, es, data): | |
300f9194 | 103 | left, right = int(self.sample_point), int(self.bit_width - self.sample_point) |
4b1813b4 UH |
104 | self.put(ss - left, es + right, self.out_ann, data) |
105 | ||
106 | # Single-CAN-bit annotation using the current samplenum. | |
e20f455c | 107 | def putx(self, data): |
4b1813b4 UH |
108 | self.putg(self.samplenum, self.samplenum, data) |
109 | ||
110 | # Single-CAN-bit annotation using the samplenum of CAN bit 12. | |
111 | def put12(self, data): | |
112 | self.putg(self.ss_bit12, self.ss_bit12, data) | |
113 | ||
6c890c08 | 114 | # Single-CAN-bit annotation using the samplenum of CAN bit 32. |
115 | def put32(self, data): | |
116 | self.putg(self.ss_bit32, self.ss_bit32, data) | |
117 | ||
4b1813b4 UH |
118 | # Multi-CAN-bit annotation from self.ss_block to current samplenum. |
119 | def putb(self, data): | |
120 | self.putg(self.ss_block, self.samplenum, data) | |
e20f455c | 121 | |
ba8529ae | 122 | def putpy(self, data): |
7ecd283c KH |
123 | self.put(self.ss_packet, self.es_packet, self.out_python, data) |
124 | ||
702fa251 UH |
125 | def reset_variables(self): |
126 | self.state = 'IDLE' | |
127 | self.sof = self.frame_type = self.dlc = None | |
128 | self.rawbits = [] # All bits, including stuff bits | |
129 | self.bits = [] # Only actual CAN frame bits (no stuff bits) | |
130 | self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF) | |
131 | self.last_databit = 999 # Positive value that bitnum+x will never match | |
4b1813b4 UH |
132 | self.ss_block = None |
133 | self.ss_bit12 = None | |
6c890c08 | 134 | self.ss_bit32 = None |
4b1813b4 | 135 | self.ss_databytebits = [] |
ba8529ae | 136 | self.frame_bytes = [] |
7ecd283c | 137 | self.rtr_type = None |
6c890c08 | 138 | self.fd = False |
139 | self.rtr = None | |
702fa251 | 140 | |
45a50880 GS |
141 | # Poor man's clock synchronization. Use signal edges which change to |
142 | # dominant state in rather simple ways. This naive approach is neither | |
143 | # aware of the SYNC phase's width nor the specific location of the edge, | |
144 | # but improves the decoder's reliability when the input signal's bitrate | |
145 | # does not exactly match the nominal rate. | |
146 | def dom_edge_seen(self, force = False): | |
147 | self.dom_edge_snum = self.samplenum | |
148 | self.dom_edge_bcount = self.curbit | |
149 | ||
64d87119 GS |
150 | # Determine the position of the next desired bit's sample point. |
151 | def get_sample_point(self, bitnum): | |
45a50880 | 152 | samplenum = self.dom_edge_snum |
e4eeaab3 GS |
153 | samplenum += self.bit_width * (bitnum - self.dom_edge_bcount) |
154 | samplenum += self.sample_point | |
155 | return int(samplenum) | |
702fa251 UH |
156 | |
157 | def is_stuff_bit(self): | |
158 | # CAN uses NRZ encoding and bit stuffing. | |
159 | # After 5 identical bits, a stuff bit of opposite value is added. | |
a0128522 | 160 | # But not in the CRC delimiter, ACK, and end of frame fields. |
cffb6592 | 161 | if len(self.bits) > self.last_databit + 17: |
a0128522 | 162 | return False |
702fa251 UH |
163 | last_6_bits = self.rawbits[-6:] |
164 | if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]): | |
165 | return False | |
166 | ||
167 | # Stuff bit. Keep it in self.rawbits, but drop it from self.bits. | |
702fa251 UH |
168 | self.bits.pop() # Drop last bit. |
169 | return True | |
170 | ||
171 | def is_valid_crc(self, crc_bits): | |
172 | return True # TODO | |
173 | ||
174 | def decode_error_frame(self, bits): | |
175 | pass # TODO | |
176 | ||
177 | def decode_overload_frame(self, bits): | |
178 | pass # TODO | |
179 | ||
180 | # Both standard and extended frames end with CRC, CRC delimiter, ACK, | |
181 | # ACK delimiter, and EOF fields. Handle them in a common function. | |
182 | # Returns True if the frame ended (EOF), False otherwise. | |
183 | def decode_frame_end(self, can_rx, bitnum): | |
184 | ||
4b1813b4 UH |
185 | # Remember start of CRC sequence (see below). |
186 | if bitnum == (self.last_databit + 1): | |
187 | self.ss_block = self.samplenum | |
741dba78 | 188 | if self.fd: |
ad373029 | 189 | if dlc2len(self.dlc) < 16: |
741dba78 ST |
190 | self.crc_len = 27 # 17 + SBC + stuff bits |
191 | else: | |
fd41596a | 192 | self.crc_len = 32 # 21 + SBC + stuff bits |
741dba78 ST |
193 | else: |
194 | self.crc_len = 15 | |
195 | ||
196 | # CRC sequence (15 bits, 17 bits or 21 bits) | |
197 | elif bitnum == (self.last_databit + self.crc_len): | |
198 | if self.fd: | |
ad373029 | 199 | if dlc2len(self.dlc) < 16: |
3b593817 UH |
200 | crc_type = "CRC-17" |
201 | else: | |
202 | crc_type = "CRC-21" | |
741dba78 | 203 | else: |
9a76aa18 | 204 | crc_type = "CRC-15" |
741dba78 | 205 | |
702fa251 | 206 | x = self.last_databit + 1 |
741dba78 | 207 | crc_bits = self.bits[x:x + self.crc_len + 1] |
b0edaeb3 GS |
208 | bits = crc_bits |
209 | bits.reverse() | |
210 | self.crc = bitpack(bits) | |
741dba78 ST |
211 | self.putb([11, ['%s sequence: 0x%04x' % (crc_type, self.crc), |
212 | '%s: 0x%04x' % (crc_type, self.crc), '%s' % crc_type]]) | |
702fa251 | 213 | if not self.is_valid_crc(crc_bits): |
74c9bb3c | 214 | self.putb([16, ['CRC is invalid']]) |
702fa251 UH |
215 | |
216 | # CRC delimiter bit (recessive) | |
741dba78 | 217 | elif bitnum == (self.last_databit + self.crc_len + 1): |
74c9bb3c UH |
218 | self.putx([12, ['CRC delimiter: %d' % can_rx, |
219 | 'CRC d: %d' % can_rx, 'CRC d']]) | |
2fac4493 UH |
220 | if can_rx != 1: |
221 | self.putx([16, ['CRC delimiter must be a recessive bit']]) | |
702fa251 | 222 | |
8abd7aa3 ST |
223 | if self.fd: |
224 | self.set_nominal_bitrate() | |
225 | ||
702fa251 | 226 | # ACK slot bit (dominant: ACK, recessive: NACK) |
741dba78 | 227 | elif bitnum == (self.last_databit + self.crc_len + 2): |
702fa251 | 228 | ack = 'ACK' if can_rx == 0 else 'NACK' |
74c9bb3c | 229 | self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']]) |
702fa251 UH |
230 | |
231 | # ACK delimiter bit (recessive) | |
741dba78 | 232 | elif bitnum == (self.last_databit + self.crc_len + 3): |
74c9bb3c UH |
233 | self.putx([14, ['ACK delimiter: %d' % can_rx, |
234 | 'ACK d: %d' % can_rx, 'ACK d']]) | |
2fac4493 UH |
235 | if can_rx != 1: |
236 | self.putx([16, ['ACK delimiter must be a recessive bit']]) | |
702fa251 | 237 | |
4b1813b4 | 238 | # Remember start of EOF (see below). |
741dba78 | 239 | elif bitnum == (self.last_databit + self.crc_len + 4): |
4b1813b4 UH |
240 | self.ss_block = self.samplenum |
241 | ||
702fa251 | 242 | # End of frame (EOF), 7 recessive bits |
b177af15 | 243 | elif bitnum == (self.last_databit + self.crc_len + 10): |
74c9bb3c | 244 | self.putb([2, ['End of frame', 'EOF', 'E']]) |
2fac4493 UH |
245 | if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]: |
246 | self.putb([16, ['End of frame (EOF) must be 7 recessive bits']]) | |
7ecd283c | 247 | self.es_packet = self.samplenum |
ba8529ae GS |
248 | py_data = tuple([self.frame_type, self.fullid, self.rtr_type, |
249 | self.dlc, self.frame_bytes]) | |
250 | self.putpy(py_data) | |
702fa251 UH |
251 | self.reset_variables() |
252 | return True | |
253 | ||
254 | return False | |
255 | ||
256 | # Returns True if the frame ended (EOF), False otherwise. | |
257 | def decode_standard_frame(self, can_rx, bitnum): | |
258 | ||
3b593817 UH |
259 | # Bit 14: FDF (Flexible data format) |
260 | # Has to be sent dominant when FD frame, has to be sent recessive | |
261 | # when classic CAN frame. | |
702fa251 | 262 | if bitnum == 14: |
38b40330 | 263 | self.fd = True if can_rx else False |
b177af15 | 264 | if self.fd: |
3b593817 UH |
265 | self.putx([7, ['Flexible data format: %d' % can_rx, |
266 | 'FDF: %d' % can_rx, 'FDF']]) | |
b177af15 ST |
267 | else: |
268 | self.putx([7, ['Reserved bit 0: %d' % can_rx, | |
3b593817 | 269 | 'RB0: %d' % can_rx, 'RB0']]) |
38b40330 | 270 | |
38b40330 | 271 | if self.fd: |
3b593817 UH |
272 | # Bit 12: Substitute remote request (SRR) bit |
273 | self.put12([8, ['Substitute remote request', 'SRR']]) | |
7f75d507 | 274 | self.dlc_start = 18 |
38b40330 ST |
275 | else: |
276 | # Bit 12: Remote transmission request (RTR) bit | |
277 | # Data frame: dominant, remote frame: recessive | |
278 | # Remote frames do not contain a data field. | |
ba8529ae GS |
279 | rtr = 'remote' if self.bits[12] == 1 else 'data' |
280 | self.put12([8, ['Remote transmission request: %s frame' % rtr, | |
281 | 'RTR: %s frame' % rtr, 'RTR']]) | |
282 | self.rtr_type = rtr | |
7f75d507 | 283 | self.dlc_start = 15 |
38b40330 | 284 | |
3b593817 UH |
285 | if bitnum == 15 and self.fd: |
286 | self.putx([7, ['Reserved: %d' % can_rx, 'R0: %d' % can_rx, 'R0']]) | |
7f75d507 | 287 | |
3b593817 UH |
288 | if bitnum == 16 and self.fd: |
289 | self.putx([7, ['Bit rate switch: %d' % can_rx, 'BRS: %d' % can_rx, 'BRS']]) | |
702fa251 | 290 | |
3b593817 UH |
291 | if bitnum == 17 and self.fd: |
292 | self.putx([7, ['Error state indicator: %d' % can_rx, 'ESI: %d' % can_rx, 'ESI']]) | |
4b1813b4 UH |
293 | |
294 | # Remember start of DLC (see below). | |
7f75d507 | 295 | elif bitnum == self.dlc_start: |
4b1813b4 | 296 | self.ss_block = self.samplenum |
702fa251 UH |
297 | |
298 | # Bits 15-18: Data length code (DLC), in number of bytes (0-8). | |
7f75d507 | 299 | elif bitnum == self.dlc_start + 3: |
b0edaeb3 GS |
300 | bits = self.bits[self.dlc_start:self.dlc_start + 4] |
301 | bits.reverse() | |
302 | self.dlc = bitpack(bits) | |
b177af15 | 303 | self.putb([10, ['Data length code: %d' % self.dlc, |
3b593817 | 304 | 'DLC: %d' % self.dlc, 'DLC']]) |
ad373029 | 305 | self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8) |
b177af15 ST |
306 | if self.dlc > 8 and not self.fd: |
307 | self.putb([16, ['Data length code (DLC) > 8 is not allowed']]) | |
702fa251 | 308 | |
4b1813b4 | 309 | # Remember all databyte bits, except the very last one. |
7f75d507 | 310 | elif bitnum in range(self.dlc_start + 4, self.last_databit): |
4b1813b4 UH |
311 | self.ss_databytebits.append(self.samplenum) |
312 | ||
702fa251 UH |
313 | # Bits 19-X: Data field (0-8 bytes, depending on DLC) |
314 | # The bits within a data byte are transferred MSB-first. | |
315 | elif bitnum == self.last_databit: | |
4b1813b4 | 316 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
ad373029 | 317 | for i in range(dlc2len(self.dlc)): |
7f75d507 | 318 | x = self.dlc_start + 4 + (8 * i) |
b0edaeb3 GS |
319 | bits = self.bits[x:x + 8] |
320 | bits.reverse() | |
321 | b = bitpack(bits) | |
ba8529ae | 322 | self.frame_bytes.append(b) |
4b1813b4 UH |
323 | ss = self.ss_databytebits[i * 8] |
324 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
534ae912 UH |
325 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), |
326 | 'DB %d: 0x%02x' % (i, b), 'DB']]) | |
4b1813b4 | 327 | self.ss_databytebits = [] |
702fa251 UH |
328 | |
329 | elif bitnum > self.last_databit: | |
330 | return self.decode_frame_end(can_rx, bitnum) | |
331 | ||
332 | return False | |
333 | ||
334 | # Returns True if the frame ended (EOF), False otherwise. | |
335 | def decode_extended_frame(self, can_rx, bitnum): | |
336 | ||
4b1813b4 UH |
337 | # Remember start of EID (see below). |
338 | if bitnum == 14: | |
339 | self.ss_block = self.samplenum | |
655f8b16 | 340 | self.fd = False |
341 | self.dlc_start = 35 | |
4b1813b4 | 342 | |
702fa251 | 343 | # Bits 14-31: Extended identifier (EID[17..0]) |
4b1813b4 | 344 | elif bitnum == 31: |
b0edaeb3 GS |
345 | bits = self.bits[14:] |
346 | bits.reverse() | |
347 | self.eid = bitpack(bits) | |
534ae912 | 348 | s = '%d (0x%x)' % (self.eid, self.eid) |
74c9bb3c | 349 | self.putb([4, ['Extended Identifier: %s' % s, |
534ae912 | 350 | 'Extended ID: %s' % s, 'Extended ID', 'EID']]) |
702fa251 | 351 | |
bd7efe23 | 352 | self.fullid = self.ident << 18 | self.eid |
534ae912 | 353 | s = '%d (0x%x)' % (self.fullid, self.fullid) |
74c9bb3c | 354 | self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s, |
534ae912 | 355 | 'Full ID', 'FID']]) |
702fa251 UH |
356 | |
357 | # Bit 12: Substitute remote request (SRR) bit | |
74c9bb3c | 358 | self.put12([9, ['Substitute remote request: %d' % self.bits[12], |
534ae912 | 359 | 'SRR: %d' % self.bits[12], 'SRR']]) |
702fa251 UH |
360 | |
361 | # Bit 32: Remote transmission request (RTR) bit | |
362 | # Data frame: dominant, remote frame: recessive | |
363 | # Remote frames do not contain a data field. | |
655f8b16 | 364 | |
365 | # Remember start of RTR (see below). | |
702fa251 | 366 | if bitnum == 32: |
6c890c08 | 367 | self.ss_bit32 = self.samplenum |
368 | self.rtr = can_rx | |
702fa251 | 369 | |
6c890c08 | 370 | if not self.fd: |
ba8529ae GS |
371 | rtr = 'remote' if can_rx == 1 else 'data' |
372 | self.putx([8, ['Remote transmission request: %s frame' % rtr, | |
373 | 'RTR: %s frame' % rtr, 'RTR']]) | |
374 | self.rtr_type = rtr | |
655f8b16 | 375 | |
702fa251 UH |
376 | # Bit 33: RB1 (reserved bit) |
377 | elif bitnum == 33: | |
655f8b16 | 378 | self.fd = True if can_rx else False |
655f8b16 | 379 | if self.fd: |
380 | self.dlc_start = 37 | |
3b593817 | 381 | self.putx([7, ['Flexible data format: %d' % can_rx, |
655f8b16 | 382 | 'FDF: %d' % can_rx, 'FDF']]) |
6c890c08 | 383 | self.put32([7, ['Reserved bit 1: %d' % self.rtr, |
384 | 'RB1: %d' % self.rtr, 'RB1']]) | |
655f8b16 | 385 | else: |
386 | self.putx([7, ['Reserved bit 1: %d' % can_rx, | |
387 | 'RB1: %d' % can_rx, 'RB1']]) | |
702fa251 UH |
388 | |
389 | # Bit 34: RB0 (reserved bit) | |
390 | elif bitnum == 34: | |
74c9bb3c | 391 | self.putx([7, ['Reserved bit 0: %d' % can_rx, |
534ae912 | 392 | 'RB0: %d' % can_rx, 'RB0']]) |
702fa251 | 393 | |
655f8b16 | 394 | elif bitnum == 35 and self.fd: |
395 | self.putx([7, ['Bit rate switch: %d' % can_rx, | |
396 | 'BRS: %d' % can_rx, 'BRS']]) | |
397 | ||
398 | elif bitnum == 36 and self.fd: | |
399 | self.putx([7, ['Error state indicator: %d' % can_rx, | |
400 | 'ESI: %d' % can_rx, 'ESI']]) | |
401 | ||
4b1813b4 | 402 | # Remember start of DLC (see below). |
655f8b16 | 403 | elif bitnum == self.dlc_start: |
4b1813b4 UH |
404 | self.ss_block = self.samplenum |
405 | ||
702fa251 | 406 | # Bits 35-38: Data length code (DLC), in number of bytes (0-8). |
655f8b16 | 407 | elif bitnum == self.dlc_start + 3: |
b0edaeb3 GS |
408 | bits = self.bits[self.dlc_start:self.dlc_start + 4] |
409 | bits.reverse() | |
410 | self.dlc = bitpack(bits) | |
b177af15 ST |
411 | self.putb([10, ['Data length code: %d' % self.dlc, |
412 | 'DLC: %d' % self.dlc, 'DLC']]) | |
ad373029 | 413 | self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8) |
702fa251 | 414 | |
4b1813b4 | 415 | # Remember all databyte bits, except the very last one. |
655f8b16 | 416 | elif bitnum in range(self.dlc_start + 4, self.last_databit): |
4b1813b4 UH |
417 | self.ss_databytebits.append(self.samplenum) |
418 | ||
702fa251 UH |
419 | # Bits 39-X: Data field (0-8 bytes, depending on DLC) |
420 | # The bits within a data byte are transferred MSB-first. | |
421 | elif bitnum == self.last_databit: | |
4b1813b4 | 422 | self.ss_databytebits.append(self.samplenum) # Last databyte bit. |
ad373029 | 423 | for i in range(dlc2len(self.dlc)): |
655f8b16 | 424 | x = self.dlc_start + 4 + (8 * i) |
b0edaeb3 GS |
425 | bits = self.bits[x:x + 8] |
426 | bits.reverse() | |
427 | b = bitpack(bits) | |
ba8529ae | 428 | self.frame_bytes.append(b) |
4b1813b4 UH |
429 | ss = self.ss_databytebits[i * 8] |
430 | es = self.ss_databytebits[((i + 1) * 8) - 1] | |
534ae912 UH |
431 | self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), |
432 | 'DB %d: 0x%02x' % (i, b), 'DB']]) | |
4b1813b4 | 433 | self.ss_databytebits = [] |
702fa251 UH |
434 | |
435 | elif bitnum > self.last_databit: | |
436 | return self.decode_frame_end(can_rx, bitnum) | |
437 | ||
438 | return False | |
439 | ||
440 | def handle_bit(self, can_rx): | |
441 | self.rawbits.append(can_rx) | |
442 | self.bits.append(can_rx) | |
443 | ||
444 | # Get the index of the current CAN frame bit (without stuff bits). | |
445 | bitnum = len(self.bits) - 1 | |
446 | ||
8abd7aa3 ST |
447 | if self.fd and can_rx: |
448 | if bitnum == 16 and self.frame_type == 'standard' \ | |
449 | or bitnum == 35 and self.frame_type == 'extended': | |
450 | self.dom_edge_seen(force=True) | |
451 | self.set_fast_bitrate() | |
452 | ||
702fa251 UH |
453 | # If this is a stuff bit, remove it from self.bits and ignore it. |
454 | if self.is_stuff_bit(): | |
544038d9 | 455 | self.putx([15, [str(can_rx)]]) |
702fa251 UH |
456 | self.curbit += 1 # Increase self.curbit (bitnum is not affected). |
457 | return | |
544038d9 UH |
458 | else: |
459 | self.putx([17, [str(can_rx)]]) | |
702fa251 UH |
460 | |
461 | # Bit 0: Start of frame (SOF) bit | |
462 | if bitnum == 0: | |
7ecd283c | 463 | self.ss_packet = self.samplenum |
2fac4493 UH |
464 | self.putx([1, ['Start of frame', 'SOF', 'S']]) |
465 | if can_rx != 0: | |
74c9bb3c | 466 | self.putx([16, ['Start of frame (SOF) must be a dominant bit']]) |
702fa251 | 467 | |
4b1813b4 UH |
468 | # Remember start of ID (see below). |
469 | elif bitnum == 1: | |
470 | self.ss_block = self.samplenum | |
471 | ||
702fa251 UH |
472 | # Bits 1-11: Identifier (ID[10..0]) |
473 | # The bits ID[10..4] must NOT be all recessive. | |
474 | elif bitnum == 11: | |
b0edaeb3 GS |
475 | bits = self.bits[1:] |
476 | bits.reverse() | |
bd7efe23 GS |
477 | # BEWARE! Don't clobber the decoder's .id field which is |
478 | # part of its boiler plate! | |
479 | self.ident = bitpack(bits) | |
480 | self.fullid = self.ident | |
481 | s = '%d (0x%x)' % (self.ident, self.ident), | |
74c9bb3c | 482 | self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']]) |
bd7efe23 | 483 | if (self.ident & 0x7f0) == 0x7f0: |
2fac4493 | 484 | self.putb([16, ['Identifier bits 10..4 must not be all recessive']]) |
702fa251 UH |
485 | |
486 | # RTR or SRR bit, depending on frame type (gets handled later). | |
487 | elif bitnum == 12: | |
4b1813b4 UH |
488 | # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only. |
489 | self.ss_bit12 = self.samplenum | |
702fa251 UH |
490 | |
491 | # Bit 13: Identifier extension (IDE) bit | |
492 | # Standard frame: dominant, extended frame: recessive | |
493 | elif bitnum == 13: | |
494 | ide = self.frame_type = 'standard' if can_rx == 0 else 'extended' | |
74c9bb3c | 495 | self.putx([6, ['Identifier extension bit: %s frame' % ide, |
534ae912 | 496 | 'IDE: %s frame' % ide, 'IDE']]) |
702fa251 UH |
497 | |
498 | # Bits 14-X: Frame-type dependent, passed to the resp. handlers. | |
499 | elif bitnum >= 14: | |
500 | if self.frame_type == 'standard': | |
501 | done = self.decode_standard_frame(can_rx, bitnum) | |
502 | else: | |
503 | done = self.decode_extended_frame(can_rx, bitnum) | |
504 | ||
505 | # The handlers return True if a frame ended (EOF). | |
506 | if done: | |
507 | return | |
508 | ||
509 | # After a frame there are 3 intermission bits (recessive). | |
510 | # After these bits, the bus is considered free. | |
511 | ||
512 | self.curbit += 1 | |
513 | ||
64d87119 | 514 | def decode(self): |
21cda951 UH |
515 | if not self.samplerate: |
516 | raise SamplerateError('Cannot decode without samplerate.') | |
702fa251 | 517 | |
64d87119 | 518 | while True: |
702fa251 UH |
519 | # State machine. |
520 | if self.state == 'IDLE': | |
521 | # Wait for a dominant state (logic 0) on the bus. | |
64d87119 | 522 | (can_rx,) = self.wait({0: 'l'}) |
702fa251 | 523 | self.sof = self.samplenum |
45a50880 | 524 | self.dom_edge_seen(force = True) |
702fa251 UH |
525 | self.state = 'GET BITS' |
526 | elif self.state == 'GET BITS': | |
527 | # Wait until we're in the correct bit/sampling position. | |
64d87119 | 528 | pos = self.get_sample_point(self.curbit) |
45a50880 GS |
529 | (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}]) |
530 | if self.matched[1]: | |
531 | self.dom_edge_seen() | |
532 | if self.matched[0]: | |
533 | self.handle_bit(can_rx) |