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1d4fe1c1 JH |
1 | ## |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2017 Joel Holdsworth <joel@airwebreathe.org.uk> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 3 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | ## | |
19 | ||
20 | import sigrokdecode as srd | |
317eaa7f | 21 | from common.srdhelper import bitpack_lsb |
1d4fe1c1 JH |
22 | |
23 | def disabled_enabled(v): | |
24 | return ['Disabled', 'Enabled'][v] | |
25 | ||
26 | def output_power(v): | |
27 | return '%+ddBm' % [-4, -1, 2, 5][v] | |
28 | ||
29 | regs = { | |
30 | # reg: name offset width parser | |
31 | 0: [ | |
32 | ('FRAC', 3, 12, None), | |
33 | ('INT', 15, 16, lambda v: 'Not Allowed' if v < 32 else v) | |
34 | ], | |
35 | 1: [ | |
36 | ('MOD', 3, 12, None), | |
37 | ('Phase', 15, 12, None), | |
38 | ('Prescalar', 27, 1, lambda v: ['4/5', '8/9'][v]), | |
39 | ('Phase Adjust', 28, 1, lambda v: ['Off', 'On'][v]), | |
40 | ], | |
41 | 2: [ | |
42 | ('Counter Reset', 3, 1, disabled_enabled), | |
43 | ('Charge Pump Three-State', 4, 1, disabled_enabled), | |
44 | ('Power-Down', 5, 1, disabled_enabled), | |
45 | ('PD Polarity', 6, 1, lambda v: ['Negative', 'Positive'][v]), | |
46 | ('LDP', 7, 1, lambda v: ['10ns', '6ns'][v]), | |
47 | ('LDF', 8, 1, lambda v: ['FRAC-N', 'INT-N'][v]), | |
48 | ('Charge Pump Current Setting', 9, 4, lambda v: '%0.2fmA @ 5.1kΩ' % | |
49 | [0.31, 0.63, 0.94, 1.25, 1.56, 1.88, 2.19, 2.50, | |
50 | 2.81, 3.13, 3.44, 3.75, 4.06, 4.38, 4.69, 5.00][v]), | |
51 | ('Double Buffer', 13, 1, disabled_enabled), | |
52 | ('R Counter', 14, 10, None), | |
53 | ('RDIV2', 24, 1, disabled_enabled), | |
54 | ('Reference Doubler', 25, 1, disabled_enabled), | |
55 | ('MUXOUT', 26, 3, lambda v: | |
56 | ['Three-State Output', 'DVdd', 'DGND', 'R Counter Output', 'N Divider Output', | |
57 | 'Analog Lock Detect', 'Digital Lock Detect', 'Reserved'][v]), | |
58 | ('Low Noise and Low Spur Modes', 29, 2, lambda v: | |
59 | ['Low Noise Mode', 'Reserved', 'Reserved', 'Low Spur Mode'][v]) | |
60 | ], | |
61 | 3: [ | |
62 | ('Clock Divider', 3, 12, None), | |
63 | ('Clock Divider Mode', 15, 2, lambda v: | |
64 | ['Clock Divider Off', 'Fast Lock Enable', 'Resync Enable', 'Reserved'][v]), | |
65 | ('CSR Enable', 18, 1, disabled_enabled), | |
66 | ('Charge Cancellation', 21, 1, disabled_enabled), | |
67 | ('ABP', 22, 1, lambda v: ['6ns (FRAC-N)', '3ns (INT-N)'][v]), | |
68 | ('Band Select Clock Mode', 23, 1, lambda v: ['Low', 'High'][v]) | |
69 | ], | |
70 | 4: [ | |
71 | ('Output Power', 3, 2, output_power), | |
72 | ('Output Enable', 5, 1, disabled_enabled), | |
73 | ('AUX Output Power', 6, 2, output_power), | |
74 | ('AUX Output Select', 8, 1, lambda v: ['Divided Output', 'Fundamental'][v]), | |
75 | ('AUX Output Enable', 9, 1, disabled_enabled), | |
76 | ('MTLD', 10, 1, disabled_enabled), | |
77 | ('VCO Power-Down', 11, 1, lambda v: | |
78 | 'VCO Powered ' + ('Down' if v == 1 else 'Up')), | |
79 | ('Band Select Clock Divider', 12, 8, None), | |
80 | ('RF Divider Select', 20, 3, lambda v: '÷' + str(2**v)), | |
81 | ('Feedback Select', 23, 1, lambda v: ['Divided', 'Fundamental'][v]), | |
82 | ], | |
83 | 5: [ | |
84 | ('LD Pin Mode', 22, 2, lambda v: | |
85 | ['Low', 'Digital Lock Detect', 'Low', 'High'][v]) | |
86 | ] | |
87 | } | |
88 | ||
89 | ANN_REG = 0 | |
f534ce44 | 90 | ANN_WARN = 1 |
1d4fe1c1 JH |
91 | |
92 | class Decoder(srd.Decoder): | |
b197383c | 93 | api_version = 3 |
1d4fe1c1 JH |
94 | id = 'adf435x' |
95 | name = 'ADF435x' | |
96 | longname = 'Analog Devices ADF4350/1' | |
97 | desc = 'Wideband synthesizer with integrated VCO.' | |
98 | license = 'gplv3+' | |
99 | inputs = ['spi'] | |
6cbba91f | 100 | outputs = [] |
d6d8a8a4 | 101 | tags = ['Clock/timing', 'IC', 'Wireless/RF'] |
1d4fe1c1 JH |
102 | annotations = ( |
103 | # Sent from the host to the chip. | |
e144452b | 104 | ('write', 'Register write'), |
f534ce44 | 105 | ('warning', "Warnings"), |
1d4fe1c1 JH |
106 | ) |
107 | annotation_rows = ( | |
e144452b | 108 | ('writes', 'Register writes', (ANN_REG,)), |
f534ce44 | 109 | ('warnings', 'Warnings', (ANN_WARN,)), |
1d4fe1c1 JH |
110 | ) |
111 | ||
112 | def __init__(self): | |
10aeb8ea GS |
113 | self.reset() |
114 | ||
115 | def reset(self): | |
1d4fe1c1 JH |
116 | self.bits = [] |
117 | ||
118 | def start(self): | |
119 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
120 | ||
121 | def decode_bits(self, offset, width): | |
317eaa7f GS |
122 | bits = self.bits[offset:][:width] |
123 | ss, es = bits[-1][1], bits[0][2] | |
124 | value = bitpack_lsb(bits, 0) | |
125 | return ( value, ( ss, es, )) | |
1d4fe1c1 JH |
126 | |
127 | def decode_field(self, name, offset, width, parser): | |
128 | val, pos = self.decode_bits(offset, width) | |
129 | self.put(pos[0], pos[1], self.out_ann, [ANN_REG, | |
130 | ['%s: %s' % (name, parser(val) if parser else str(val))]]) | |
131 | return val | |
132 | ||
133 | def decode(self, ss, es, data): | |
53cbedf5 | 134 | ptype, _, _ = data |
1d4fe1c1 | 135 | |
adb8233a VPP |
136 | if ptype == 'TRANSFER': |
137 | if len(self.bits) == 32: | |
912f4e8a | 138 | self.bits.reverse() |
adb8233a VPP |
139 | reg_value, reg_pos = self.decode_bits(0, 3) |
140 | self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG, | |
141 | ['Register: %d' % reg_value, 'Reg: %d' % reg_value, | |
142 | '[%d]' % reg_value]]) | |
143 | if reg_value < len(regs): | |
144 | field_descs = regs[reg_value] | |
145 | for field_desc in field_descs: | |
146 | field = self.decode_field(*field_desc) | |
f534ce44 | 147 | else: |
adb8233a VPP |
148 | error = "Frame error: Wrong number of bits: got %d expected 32" % len(self.bits) |
149 | self.put(ss, es, self.out_ann, [ANN_WARN, [error, 'Frame error']]) | |
912f4e8a | 150 | self.bits.clear() |
f534ce44 | 151 | |
1d4fe1c1 | 152 | if ptype == 'BITS': |
53cbedf5 | 153 | _, mosi_bits, miso_bits = data |
912f4e8a GS |
154 | # Cope with the lower layer SPI decoder's output convention: |
155 | # Regardless of wire transfer's frame format, .decode() input | |
156 | # provides BITS in the LE order. Accumulate in MSB order here, | |
157 | # and reverse before data processing when 'TRANSFER' is seen. | |
158 | mosi_bits = mosi_bits.copy() | |
159 | mosi_bits.reverse() | |
160 | self.bits.extend(mosi_bits) |