FPGA configuration (netlist upload) of ASIX SIGMA devices is rather
special a phase, and deserves its own state in the device context's
"state" tracking. Not only is the logic analyzer not available during
this period, the FTDI cable is also put into bitbanging mode instead
of regular data communication in FIFO mode, and netlist configuration
takes a considerable amount of time (tenths of a second).
+ devc->state.state = SIGMA_CONFIG;
+
/* Set the cable to bitbang mode. */
ret = ftdi_set_bitmode(&devc->ftdic, BB_PINMASK, BITMODE_BITBANG);
if (ret < 0) {
/* Set the cable to bitbang mode. */
ret = ftdi_set_bitmode(&devc->ftdic, BB_PINMASK, BITMODE_BITBANG);
if (ret < 0) {
return ret;
/* Keep track of successful firmware download completion. */
return ret;
/* Keep track of successful firmware download completion. */
+ devc->state.state = SIGMA_IDLE;
devc->cur_firmware = firmware_idx;
sr_info("Firmware uploaded.");
devc->cur_firmware = firmware_idx;
sr_info("Firmware uploaded.");
if (ret == SR_OK) {
devc->num_channels = num_channels;
devc->samples_per_event = 16 / devc->num_channels;
if (ret == SR_OK) {
devc->num_channels = num_channels;
devc->samples_per_event = 16 / devc->num_channels;
- devc->state.state = SIGMA_IDLE;
struct sigma_state {
enum {
SIGMA_UNINITIALIZED = 0,
struct sigma_state {
enum {
SIGMA_UNINITIALIZED = 0,
SIGMA_IDLE,
SIGMA_CAPTURE,
SIGMA_STOPPING,
SIGMA_IDLE,
SIGMA_CAPTURE,
SIGMA_STOPPING,