+static const uint32_t scanopts[] = {
+ SR_CONF_CONN,
+};
+
+static const uint32_t drvopts[] = {
+ SR_CONF_SIGNAL_GENERATOR,
+};
+
+static const uint32_t dg1000z_devopts[] = {
+ SR_CONF_CONTINUOUS,
+ SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
+};
+
+static const uint32_t dg1000z_devopts_cg[] = {
+ SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_AMPLITUDE | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_OFFSET | SR_CONF_GET | SR_CONF_SET,
+ SR_CONF_PHASE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+ SR_CONF_DUTY_CYCLE | SR_CONF_GET | SR_CONF_SET,
+};
+
+static const double phase_min_max_step[] = { 0.0, 360.0, 0.001 };
+
+#define WAVEFORM_DEFAULT WFO_FREQUENCY | WFO_AMPLITUDE | WFO_OFFSET | WFO_PHASE
+
+static const struct waveform_spec dg1022z_waveforms[] = {
+ { "SIN", WF_SINE, 1.0E-6, 2.5E+7, 1.0E-6, WAVEFORM_DEFAULT },
+ { "SQU", WF_SQUARE, 1.0E-6, 2.5E+7, 1.0E-6, WAVEFORM_DEFAULT | WFO_DUTY_CYCLE },
+ { "RAMP", WF_RAMP, 1.0E-6, 0.5E+6, 1.0E-6, WAVEFORM_DEFAULT },
+ { "PULSE", WF_PULSE, 1.0E-6, 1.5E+7, 1.0E-6, WAVEFORM_DEFAULT | WFO_DUTY_CYCLE },
+ { "USER", WF_ARB, 1.0E-6, 1.0E+7, 1.0E-6, WAVEFORM_DEFAULT },
+ { "NOISE", WF_NOISE, 2.5E+7, 2.5E+7, 0.0E-0, WFO_AMPLITUDE | WFO_OFFSET },
+ { "DC", WF_DC, 0.0E-0, 0.0E+0, 0.0E-0, WFO_OFFSET },
+};
+
+static const struct channel_spec dg1022z_channels[] = {
+ { "CH1", ARRAY_AND_SIZE(dg1022z_waveforms) },
+ { "CH2", ARRAY_AND_SIZE(dg1022z_waveforms) },
+};
+
+static const struct waveform_spec dg1032z_waveforms[] = {
+ { "SIN", WF_SINE, 1.0E-6, 3.0E+7, 1.0E-6, WAVEFORM_DEFAULT },
+ { "SQU", WF_SQUARE, 1.0E-6, 2.5E+7, 1.0E-6, WAVEFORM_DEFAULT | WFO_DUTY_CYCLE },
+ { "RAMP", WF_RAMP, 1.0E-6, 0.5E+6, 1.0E-6, WAVEFORM_DEFAULT },
+ { "PULSE", WF_PULSE, 1.0E-6, 1.5E+7, 1.0E-6, WAVEFORM_DEFAULT | WFO_DUTY_CYCLE },
+ { "USER", WF_ARB, 1.0E-6, 1.0E+7, 1.0E-6, WAVEFORM_DEFAULT },
+ { "NOISE", WF_NOISE, 3.0E+7, 3.0E+7, 0.0E-0, WFO_AMPLITUDE | WFO_OFFSET },
+ { "DC", WF_DC, 0.0E-0, 0.0E+0, 0.0E-0, WFO_OFFSET },
+};
+
+static const struct channel_spec dg1032z_channels[] = {
+ { "CH1", ARRAY_AND_SIZE(dg1032z_waveforms) },
+ { "CH2", ARRAY_AND_SIZE(dg1032z_waveforms) },
+};
+
+static const struct waveform_spec dg1062z_waveforms[] = {
+ { "SIN", WF_SINE, 1.0E-6, 6.0E+7, 1.0E-6, WAVEFORM_DEFAULT },
+ { "SQU", WF_SQUARE, 1.0E-6, 2.5E+7, 1.0E-6, WAVEFORM_DEFAULT | WFO_DUTY_CYCLE },
+ { "RAMP", WF_RAMP, 1.0E-6, 1.0E+6, 1.0E-6, WAVEFORM_DEFAULT },
+ { "PULSE", WF_PULSE, 1.0E-6, 2.5E+7, 1.0E-6, WAVEFORM_DEFAULT | WFO_DUTY_CYCLE },
+ { "USER", WF_ARB, 1.0E-6, 2.0E+7, 1.0E-6, WAVEFORM_DEFAULT },
+ { "NOISE", WF_NOISE, 6.0E+7, 6.0E+7, 0.0E-0, WFO_AMPLITUDE | WFO_OFFSET },
+ { "DC", WF_DC, 0.0E-0, 0.0E+0, 0.0E-0, WFO_OFFSET },
+};
+
+static const struct channel_spec dg1062z_channels[] = {
+ { "CH1", ARRAY_AND_SIZE(dg1062z_waveforms) },
+ { "CH2", ARRAY_AND_SIZE(dg1062z_waveforms) },
+};
+
+static const struct scpi_command cmdset_dg1000z[] = {
+ { PSG_CMD_SETUP_LOCAL, "SYST:KLOC:STATE OFF", },
+/* { PSG_CMD_SELECT_CHANNEL, "SYST:CHAN:CUR CH%s", }, */
+ { PSG_CMD_GET_CHANNEL, "SYST:CHAN:CUR?", },
+ { PSG_CMD_GET_ENABLED, "OUTP%s:STATE?", },
+ { PSG_CMD_SET_ENABLE, "OUTP%s:STATE ON", },
+ { PSG_CMD_SET_DISABLE, "OUTP%s:STATE OFF", },
+ { PSG_CMD_GET_SOURCE, "SOUR%s:APPL?", },
+ { PSG_CMD_SET_SOURCE, "SOUR%s:APPL:%s", },
+ { PSG_CMD_GET_FREQUENCY, "SOUR%s:FREQ?", },
+ { PSG_CMD_SET_FREQUENCY, "SOUR%s:FREQ %f", },
+ { PSG_CMD_GET_AMPLITUDE, "SOUR%s:VOLT?", },
+ { PSG_CMD_SET_AMPLITUDE, "SOUR%s:VOLT %f", },
+ { PSG_CMD_GET_OFFSET, "SOUR%s:VOLT:OFFS?", },
+ { PSG_CMD_SET_OFFSET, "SOUR%s:VOLT:OFFS %f", },
+ { PSG_CMD_GET_PHASE, "SOUR%s:PHAS?", },
+ { PSG_CMD_SET_PHASE, "SOUR%s:PHAS %f", },
+ { PSG_CMD_GET_DCYCL_PULSE, "SOUR%s:FUNC:PULS:DCYC?", },
+ { PSG_CMD_SET_DCYCL_PULSE, "SOUR%s:FUNC:PULS:DCYC %f", },
+ { PSG_CMD_GET_DCYCL_SQUARE, "SOUR%s:FUNC:SQU:DCYC?", },
+ { PSG_CMD_SET_DCYCL_SQUARE, "SOUR%s:FUNC:SQU:DCYC %f", },
+ { PSG_CMD_COUNTER_GET_ENABLED, "COUN:STAT?", },
+ { PSG_CMD_COUNTER_SET_ENABLE, "COUN:STAT ON", },
+ { PSG_CMD_COUNTER_SET_DISABLE, "COUN:STAT OFF", },
+ { PSG_CMD_COUNTER_MEASURE, "COUN:MEAS?", },
+ ALL_ZERO
+};
+
+static const struct device_spec device_models[] = {
+ { "Rigol Technologies", "DG1022Z",
+ ARRAY_AND_SIZE(dg1000z_devopts),
+ ARRAY_AND_SIZE(dg1000z_devopts_cg),
+ ARRAY_AND_SIZE(dg1022z_channels),
+ cmdset_dg1000z,
+ },
+ { "Rigol Technologies", "DG1032Z",
+ ARRAY_AND_SIZE(dg1000z_devopts),
+ ARRAY_AND_SIZE(dg1000z_devopts_cg),
+ ARRAY_AND_SIZE(dg1032z_channels),
+ cmdset_dg1000z,
+ },
+ { "Rigol Technologies", "DG1062Z",
+ ARRAY_AND_SIZE(dg1000z_devopts),
+ ARRAY_AND_SIZE(dg1000z_devopts_cg),
+ ARRAY_AND_SIZE(dg1062z_channels),
+ cmdset_dg1000z,
+ },
+};
+
+static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)