src/hardware/zeroplus-logic-cube/analyzer.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
   5  * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or
   9  * without modification, are permitted provided that the following
  10  * conditions are met:
  11  *
  12  * * Redistributions of source code must retain the above copyright notice,
  13  *   this list of conditions and the following disclaimer.
  14  *
  15  * * Redistributions in binary form must reproduce the above copyright notice,
  16  *   this list of conditions and the following disclaimer in the documentation
  17  *   and/or other materials provided with the distribution.
  18  *
  19  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  29  *  THE POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <config.h>
  33 #include <assert.h>
  34 #include <libsigrok/libsigrok.h>
  35 #include "libsigrok-internal.h"
  36 #include "analyzer.h"
  37 #include "gl_usb.h"
  38 #include "protocol.h"
  39
  40 enum {
  41         HARD_DATA_CHECK_SUM             = 0x00,
  42         PASS_WORD,
  43
  44         DEV_ID0                         = 0x10,
  45         DEV_ID1,
  46
  47         START_STATUS                    = 0x20,
  48         DEV_STATUS                      = 0x21,
  49         FREQUENCY_REG0                  = 0x30,
  50         FREQUENCY_REG1,
  51         FREQUENCY_REG2,
  52         FREQUENCY_REG3,
  53         FREQUENCY_REG4,
  54         MEMORY_LENGTH,
  55         CLOCK_SOURCE,
  56
  57         TRIGGER_STATUS0                 = 0x40,
  58         TRIGGER_STATUS1,
  59         TRIGGER_STATUS2,
  60         TRIGGER_STATUS3,
  61         TRIGGER_STATUS4,
  62         TRIGGER_STATUS5,
  63         TRIGGER_STATUS6,
  64         TRIGGER_STATUS7,
  65         TRIGGER_STATUS8,
  66
  67         TRIGGER_COUNT0                  = 0x50,
  68         TRIGGER_COUNT1,
  69
  70         TRIGGER_LEVEL0                  = 0x55,
  71         TRIGGER_LEVEL1,
  72         TRIGGER_LEVEL2,
  73         TRIGGER_LEVEL3,
  74
  75         RAMSIZE_TRIGGERBAR_ADDRESS0     = 0x60,
  76         RAMSIZE_TRIGGERBAR_ADDRESS1,
  77         RAMSIZE_TRIGGERBAR_ADDRESS2,
  78         TRIGGERBAR_ADDRESS0,
  79         TRIGGERBAR_ADDRESS1,
  80         TRIGGERBAR_ADDRESS2,
  81         DONT_CARE_TRIGGERBAR,
  82
  83         FILTER_ENABLE                   = 0x70,
  84         FILTER_STATUS,
  85
  86         ENABLE_DELAY_TIME0              = 0x7a,
  87         ENABLE_DELAY_TIME1,
  88
  89         ENABLE_INSERT_DATA0             = 0x80,
  90         ENABLE_INSERT_DATA1,
  91         ENABLE_INSERT_DATA2,
  92         ENABLE_INSERT_DATA3,
  93         COMPRESSION_TYPE0,
  94         COMPRESSION_TYPE1,
  95
  96         TRIGGER_ADDRESS0                = 0x90,
  97         TRIGGER_ADDRESS1,
  98         TRIGGER_ADDRESS2,
  99
 100         NOW_ADDRESS0                    = 0x96,
 101         NOW_ADDRESS1,
 102         NOW_ADDRESS2,
 103
 104         STOP_ADDRESS0                   = 0x9b,
 105         STOP_ADDRESS1,
 106         STOP_ADDRESS2,
 107
 108         READ_RAM_STATUS                 = 0xa0,
 109 };
 110
 111 static int g_trigger_status[9] = { 0 };
 112 static int g_trigger_count = 1;
 113 static int g_filter_status[8] = { 0 };
 114 static int g_filter_enable = 0;
 115
 116 static int g_freq_value = 1;
 117 static int g_freq_scale = FREQ_SCALE_MHZ;
 118 static int g_memory_size = MEMORY_SIZE_8K;
 119 static int g_ramsize_triggerbar_addr = 2 * 1024;
 120 static int g_triggerbar_addr = 0;
 121 static int g_compression = COMPRESSION_NONE;
 122 static int g_thresh = 0x31; /* 1.5V */
 123
 124 /* Maybe unk specifies an "endpoint" or "register" of sorts. */
 125 static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
 126                                  unsigned char flags)
 127 {
 128         assert(unk <= 3);
 129         return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
 130 }
 131
 132 #if 0
 133 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
 134 {
 135         int reg0 = 0, divisor = 0, reg2 = 0;
 136
 137         switch (scale) {
 138         case FREQ_SCALE_MHZ: /* MHz */
 139                 if (freq >= 100 && freq <= 200) {
 140                         reg0 = freq * 0.1;
 141                         divisor = 1;
 142                         reg2 = 0;
 143                         break;
 144                 }
 145                 if (freq >= 50 && freq < 100) {
 146                         reg0 = freq * 0.2;
 147                         divisor = 2;
 148                         reg2 = 0;
 149                         break;
 150                 }
 151                 if (freq >= 10 && freq < 50) {
 152                         if (freq == 25) {
 153                                 reg0 = 25;
 154                                 divisor = 5;
 155                                 reg2 = 1;
 156                                 break;
 157                         } else {
 158                                 reg0 = freq * 0.5;
 159                                 divisor = 5;
 160                                 reg2 = 1;
 161                                 break;
 162                         }
 163                 }
 164                 if (freq >= 2 && freq < 10) {
 165                         divisor = 5;
 166                         reg0 = freq * 2;
 167                         reg2 = 2;
 168                         break;
 169                 }
 170                 if (freq == 1) {
 171                         divisor = 5;
 172                         reg2 = 16;
 173                         reg0 = 5;
 174                         break;
 175                 }
 176                 divisor = 5;
 177                 reg0 = 5;
 178                 reg2 = 64;
 179                 break;
 180         case FREQ_SCALE_HZ: /* Hz */
 181                 if (freq >= 500 && freq < 1000) {
 182                         reg0 = freq * 0.01;
 183                         divisor = 10;
 184                         reg2 = 64;
 185                         break;
 186                 }
 187                 if (freq >= 300 && freq < 500) {
 188                         reg0 = freq * 0.005 * 8;
 189                         divisor = 5;
 190                         reg2 = 67;
 191                         break;
 192                 }
 193                 if (freq >= 100 && freq < 300) {
 194                         reg0 = freq * 0.005 * 16;
 195                         divisor = 5;
 196                         reg2 = 68;
 197                         break;
 198                 }
 199                 divisor = 5;
 200                 reg0 = 5;
 201                 reg2 = 64;
 202                 break;
 203         case FREQ_SCALE_KHZ: /* kHz */
 204                 if (freq >= 500 && freq < 1000) {
 205                         reg0 = freq * 0.01;
 206                         divisor = 5;
 207                         reg2 = 17;
 208                         break;
 209                 }
 210                 if (freq >= 100 && freq < 500) {
 211                         reg0 = freq * 0.05;
 212                         divisor = 5;
 213                         reg2 = 32;
 214                         break;
 215                 }
 216                 if (freq >= 50 && freq < 100) {
 217                         reg0 = freq * 0.1;
 218                         divisor = 5;
 219                         reg2 = 33;
 220                         break;
 221                 }
 222                 if (freq >= 10 && freq < 50) {
 223                         if (freq == 25) {
 224                                 reg0 = 25;
 225                                 divisor = 5;
 226                                 reg2 = 49;
 227                                 break;
 228                         }
 229                         reg0 = freq * 0.5;
 230                         divisor = 5;
 231                         reg2 = 48;
 232                         break;
 233                 }
 234                 if (freq >= 2 && freq < 10) {
 235                         divisor = 5;
 236                         reg0 = freq * 2;
 237                         reg2 = 50;
 238                         break;
 239                 }
 240                 divisor = 5;
 241                 reg0 = 5;
 242                 reg2 = 64;
 243                 break;
 244         default:
 245                 divisor = 5;
 246                 reg0 = 5;
 247                 reg2 = 64;
 248                 break;
 249         }
 250
 251         sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
 252                "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
 253                freq, scale, divisor, reg0, 0x02, reg2);
 254
 255         if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
 256                 return -1; /* Divisor maybe? */
 257
 258         if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
 259                 return -1; /* 10 / 0.2 */
 260
 261         if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
 262                 return -1; /* Always 2 */
 263
 264         if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
 265                 return -1;
 266
 267         return 0;
 268 }
 269 #endif
 270
 271 /*
 272  * It seems that ...
 273  *      FREQUENCT_REG0 - division factor (?)
 274  *      FREQUENCT_REG1 - multiplication factor (?)
 275  *      FREQUENCT_REG4 - clock selection (?)
 276  *
 277  *      clock selection
 278  *      0  10MHz  16   1MHz  32 100kHz  48  10kHz  64   1kHz
 279  *      1   5MHz  17 500kHz  33  50kHz  49   5kHz  65  500Hz
 280  *      2 2.5MHz   .          .         50 2.5kHz  66  250Hz
 281  *      .          .          .          .         67  125Hz
 282  *      .          .          .          .         68 62.5Hz
 283  */
 284 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
 285 {
 286         struct freq_factor {
 287                 int freq;
 288                 int scale;
 289                 int sel;
 290                 int div;
 291                 int mul;
 292         };
 293
 294         static const struct freq_factor f[] = {
 295                 { 200, FREQ_SCALE_MHZ,  0,  1, 20 },
 296                 { 150, FREQ_SCALE_MHZ,  0,  1, 15 },
 297                 { 100, FREQ_SCALE_MHZ,  0,  1, 10 },
 298                 {  80, FREQ_SCALE_MHZ,  0,  2, 16 },
 299                 {  50, FREQ_SCALE_MHZ,  0,  2, 10 },
 300                 {  25, FREQ_SCALE_MHZ,  1,  5, 25 },
 301                 {  10, FREQ_SCALE_MHZ,  1,  5, 10 },
 302                 {   1, FREQ_SCALE_MHZ, 16,  5,  5 },
 303                 { 800, FREQ_SCALE_KHZ, 17,  5,  8 },
 304                 { 400, FREQ_SCALE_KHZ, 32,  5, 20 },
 305                 { 200, FREQ_SCALE_KHZ, 32,  5, 10 },
 306                 { 100, FREQ_SCALE_KHZ, 32,  5,  5 },
 307                 {  50, FREQ_SCALE_KHZ, 33,  5,  5 },
 308                 {  25, FREQ_SCALE_KHZ, 49,  5, 25 },
 309                 {   5, FREQ_SCALE_KHZ, 50,  5, 10 },
 310                 {   1, FREQ_SCALE_KHZ, 64,  5,  5 },
 311                 { 500, FREQ_SCALE_HZ,  64, 10,  5 },
 312                 { 100, FREQ_SCALE_HZ,  68,  5,  8 },
 313                 {   0, 0,              0,   0,  0 }
 314         };
 315
 316         int i;
 317
 318         for (i = 0; f[i].freq; i++) {
 319                 if (scale == f[i].scale && freq == f[i].freq)
 320                         break;
 321         }
 322         if (!f[i].freq)
 323                 return -1;
 324
 325         sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
 326                "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
 327                freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
 328
 329         if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
 330                 return -1;
 331
 332         if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
 333                 return -1;
 334
 335         if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
 336                 return -1;
 337
 338         if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
 339                 return -1;
 340
 341         return 0;
 342 }
 343
 344 static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
 345                                                    unsigned int address)
 346 {
 347         gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
 348         gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
 349         gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
 350 }
 351
 352 static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
 353                                               unsigned int address)
 354 {
 355         gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
 356         gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
 357         gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
 358 }
 359
 360 static void __analyzer_set_compression(libusb_device_handle *devh,
 361                                        unsigned int type)
 362 {
 363         gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
 364         gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
 365 }
 366
 367 static void __analyzer_set_trigger_count(libusb_device_handle *devh,
 368                                          unsigned int count)
 369 {
 370         gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
 371         gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
 372 }
 373
 374 static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
 375 {
 376         gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
 377         gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
 378         gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
 379         gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
 380 }
 381
 382 static void analyzer_set_filter(libusb_device_handle *devh)
 383 {
 384         int i;
 385         gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
 386         for (i = 0; i < 8; i++)
 387                 gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
 388 }
 389
 390 SR_PRIV void analyzer_reset(libusb_device_handle *devh)
 391 {
 392         analyzer_write_status(devh, 3, STATUS_FLAG_NONE);       // reset device
 393         analyzer_write_status(devh, 3, STATUS_FLAG_RESET);      // reset device
 394 }
 395
 396 SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
 397 {
 398         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 399         analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
 400         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 401 }
 402
 403 SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
 404 {
 405         int status;
 406
 407         while (1) {
 408                 status = gl_reg_read(devh, DEV_STATUS);
 409                 if ((!set || (status & set)) && ((status & unset) == 0))
 410                         return;
 411         }
 412 }
 413
 414 SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
 415 {
 416         analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
 417
 418         /* Prep for bulk reads */
 419         gl_reg_read_buf(devh, READ_RAM_STATUS, NULL, 0);
 420 }
 421
 422 SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
 423                        unsigned int size)
 424 {
 425         return gl_read_bulk(devh, buffer, size);
 426 }
 427
 428 SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
 429 {
 430         analyzer_write_status(devh, 3, STATUS_FLAG_20);
 431         analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
 432 }
 433
 434 SR_PRIV void analyzer_start(libusb_device_handle *devh)
 435 {
 436         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 437         analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
 438         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 439         analyzer_write_status(devh, 1, STATUS_FLAG_GO);
 440 }
 441
 442 SR_PRIV void analyzer_configure(libusb_device_handle *devh)
 443 {
 444         int i;
 445
 446         /* Write_Start_Status */
 447         analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
 448         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 449
 450         /* Start_Config_Outside_Device ? */
 451         analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
 452         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 453
 454         /* SetData_To_Frequence_Reg */
 455         __analyzer_set_freq(devh, g_freq_value, g_freq_scale);
 456
 457         /* SetMemory_Length */
 458         gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
 459
 460         /* Sele_Inside_Outside_Clock */
 461         gl_reg_write(devh, CLOCK_SOURCE, 0x03);
 462
 463         /* Set_Trigger_Status */
 464         for (i = 0; i < 9; i++)
 465                 gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
 466
 467         __analyzer_set_trigger_count(devh, g_trigger_count);
 468
 469         /* Set_Trigger_Level */
 470         gl_reg_write(devh, TRIGGER_LEVEL0, g_thresh);
 471         gl_reg_write(devh, TRIGGER_LEVEL1, g_thresh);
 472         gl_reg_write(devh, TRIGGER_LEVEL2, g_thresh);
 473         gl_reg_write(devh, TRIGGER_LEVEL3, g_thresh);
 474
 475         /* Size of actual memory >> 2 */
 476         __analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
 477         __analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
 478
 479         /* Set_Dont_Care_TriggerBar */
 480         gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
 481
 482         /* Enable_Status */
 483         analyzer_set_filter(devh);
 484
 485         /* Set_Enable_Delay_Time */
 486         gl_reg_write(devh, 0x7a, 0x00);
 487         gl_reg_write(devh, 0x7b, 0x00);
 488         analyzer_write_enable_insert_data(devh);
 489         __analyzer_set_compression(devh, g_compression);
 490 }
 491
 492 SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi)
 493 {
 494         struct dev_context *devc;
 495         struct sr_trigger *trigger;
 496         struct sr_trigger_stage *stage;
 497         struct sr_trigger_match *match;
 498         GSList *l, *m;
 499         int channel;
 500
 501         devc = sdi->priv;
 502
 503         if (!(trigger = sr_session_trigger_get(sdi->session)))
 504                 return SR_OK;
 505
 506         for (l = trigger->stages; l; l = l->next) {
 507                 stage = l->data;
 508                 for (m = stage->matches; m; m = m->next) {
 509                         match = m->data;
 510                         devc->trigger = 1;
 511                         if (!match->channel->enabled)
 512                                 /* Ignore disabled channels with a trigger. */
 513                                 continue;
 514                         channel = match->channel->index;
 515                         switch (match->match) {
 516                         case SR_TRIGGER_ZERO:
 517                                 g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2);
 518                                 break;
 519                         case SR_TRIGGER_ONE:
 520                                 g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2);
 521                                 break;
 522                         default:
 523                                 sr_err("Unsupported match %d", match->match);
 524                                 return SR_ERR;
 525                         }
 526                 }
 527         }
 528
 529         return SR_OK;
 530 }
 531
 532 SR_PRIV void analyzer_add_filter(int channel, int type)
 533 {
 534         int i;
 535
 536         if (type != FILTER_HIGH && type != FILTER_LOW)
 537                 return;
 538         if ((channel & 0xf) >= 8)
 539                 return;
 540
 541         if (channel & CHANNEL_A)
 542                 i = 0;
 543         else if (channel & CHANNEL_B)
 544                 i = 2;
 545         else if (channel & CHANNEL_C)
 546                 i = 4;
 547         else if (channel & CHANNEL_D)
 548                 i = 6;
 549         else
 550                 return;
 551
 552         if ((channel & 0xf) >= 4) {
 553                 i++;
 554                 channel -= 4;
 555         }
 556
 557         g_filter_status[i] |=
 558             1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
 559
 560         g_filter_enable = 1;
 561 }
 562
 563 SR_PRIV void analyzer_set_trigger_count(int count)
 564 {
 565         g_trigger_count = count;
 566 }
 567
 568 SR_PRIV void analyzer_set_freq(int freq, int scale)
 569 {
 570         g_freq_value = freq;
 571         g_freq_scale = scale;
 572 }
 573
 574 SR_PRIV void analyzer_set_memory_size(unsigned int size)
 575 {
 576         g_memory_size = size;
 577 }
 578
 579 SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
 580 {
 581         g_ramsize_triggerbar_addr = address;
 582 }
 583
 584 SR_PRIV unsigned int analyzer_get_ramsize_trigger_address(void)
 585 {
 586         return g_ramsize_triggerbar_addr;
 587 }
 588
 589 SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
 590 {
 591         g_triggerbar_addr = address;
 592 }
 593
 594 SR_PRIV unsigned int analyzer_get_triggerbar_address(void)
 595 {
 596         return g_triggerbar_addr;
 597 }
 598
 599 SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
 600 {
 601         return gl_reg_read(devh, DEV_STATUS);
 602 }
 603
 604 SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
 605 {
 606         return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
 607 }
 608
 609 SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
 610 {
 611         return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
 612                         STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
 613 }
 614
 615 SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
 616 {
 617         return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
 618                         NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
 619 }
 620
 621 SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
 622 {
 623         return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
 624                 TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
 625 }
 626
 627 SR_PRIV void analyzer_set_compression(unsigned int type)
 628 {
 629         g_compression = type;
 630 }
 631
 632 SR_PRIV void analyzer_set_voltage_threshold(int thresh)
 633 {
 634         g_thresh = thresh;
 635 }
 636
 637 SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
 638 {
 639         analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
 640 }
 641
 642 SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
 643 {
 644         analyzer_wait(devh, 0, STATUS_BUSY);
 645 }
 646
 647 SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
 648                                 void *output, unsigned int output_len)
 649 {
 650         unsigned char *in = input;
 651         unsigned char *out = output;
 652         unsigned int A, B, C, count;
 653         unsigned int written = 0;
 654
 655         while (input_len > 0) {
 656                 A = *in++;
 657                 B = *in++;
 658                 C = *in++;
 659                 count = (*in++) + 1;
 660
 661                 if (count > output_len)
 662                         count = output_len;
 663                 output_len -= count;
 664                 written += count;
 665
 666                 while (count--) {
 667                         *out++ = A;
 668                         *out++ = B;
 669                         *out++ = C;
 670                         *out++ = 0; /* Channel D */
 671                 }
 672
 673                 input_len -= 4;
 674                 if (output_len == 0)
 675                         break;
 676         }
 677
 678         return written;
 679 }