2 * This file is part of the libsigrok project.
4 * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 /* Bit mask for the RLE repeat-count-follows flag. */
24 #define RLE_FLAG_LEN_FOLLOWS ((uint64_t)1 << 35)
26 /* Start address of capture status memory area to read. */
27 #define CAP_STAT_ADDR 5
29 /* Number of 64-bit words read from the capture status memory. */
30 #define CAP_STAT_LEN 5
32 /* The bitstream filenames are indexed by the clock_config enumeration.
34 static const char bitstream_map[][32] = {
35 "sysclk-lwla1034-off.rbf",
36 "sysclk-lwla1034-int.rbf",
37 "sysclk-lwla1034-extpos.rbf",
38 "sysclk-lwla1034-extneg.rbf",
41 /* Submit an already filled-in USB transfer.
43 static int submit_transfer(struct dev_context *devc,
44 struct libusb_transfer *xfer)
48 ret = libusb_submit_transfer(xfer);
51 sr_err("Submit transfer failed: %s.", libusb_error_name(ret));
52 devc->transfer_error = TRUE;
59 /* Set up the LWLA in preparation for an acquisition session.
61 static int capture_setup(const struct sr_dev_inst *sdi)
63 struct dev_context *devc;
64 struct acquisition_state *acq;
65 uint64_t divider_count;
66 uint64_t trigger_mask;
67 uint64_t memory_limit;
68 uint16_t command[3 + (10 * 4)];
71 acq = devc->acquisition;
73 command[0] = LWLA_WORD(CMD_CAP_SETUP);
74 command[1] = LWLA_WORD(0); /* address */
75 command[2] = LWLA_WORD(10); /* length */
77 command[3] = LWLA_WORD_0(devc->channel_mask);
78 command[4] = LWLA_WORD_1(devc->channel_mask);
79 command[5] = LWLA_WORD_2(devc->channel_mask);
80 command[6] = LWLA_WORD_3(devc->channel_mask);
82 /* Set the clock divide counter maximum for samplerates of up to
83 * 100 MHz. At the highest samplerate of 125 MHz the clock divider
86 if (!acq->bypass_clockdiv && devc->samplerate > 0)
87 divider_count = SR_MHZ(100) / devc->samplerate - 1;
91 command[7] = LWLA_WORD_0(divider_count);
92 command[8] = LWLA_WORD_1(divider_count);
93 command[9] = LWLA_WORD_2(divider_count);
94 command[10] = LWLA_WORD_3(divider_count);
96 command[11] = LWLA_WORD_0(devc->trigger_values);
97 command[12] = LWLA_WORD_1(devc->trigger_values);
98 command[13] = LWLA_WORD_2(devc->trigger_values);
99 command[14] = LWLA_WORD_3(devc->trigger_values);
101 command[15] = LWLA_WORD_0(devc->trigger_edge_mask);
102 command[16] = LWLA_WORD_1(devc->trigger_edge_mask);
103 command[17] = LWLA_WORD_2(devc->trigger_edge_mask);
104 command[18] = LWLA_WORD_3(devc->trigger_edge_mask);
106 trigger_mask = devc->trigger_mask;
107 /* Set bits to select external TRG input edge. */
108 if (devc->cfg_trigger_source == TRIGGER_EXT_TRG)
109 switch (devc->cfg_trigger_slope) {
111 trigger_mask |= (uint64_t)1 << 35;
114 trigger_mask |= (uint64_t)1 << 34;
118 command[19] = LWLA_WORD_0(trigger_mask);
119 command[20] = LWLA_WORD_1(trigger_mask);
120 command[21] = LWLA_WORD_2(trigger_mask);
121 command[22] = LWLA_WORD_3(trigger_mask);
123 /* Set the capture memory full threshold. This is slightly less
124 * than the actual maximum, most likely in order to compensate for
127 memory_limit = MEMORY_DEPTH - 16;
129 command[23] = LWLA_WORD_0(memory_limit);
130 command[24] = LWLA_WORD_1(memory_limit);
131 command[25] = LWLA_WORD_2(memory_limit);
132 command[26] = LWLA_WORD_3(memory_limit);
134 /* Fill remaining 64-bit words with zeroes. */
135 memset(&command[27], 0, 16 * sizeof(uint16_t));
137 return lwla_send_command(sdi->conn, command, ARRAY_SIZE(command));
140 /* Issue a register write command as an asynchronous USB transfer.
142 static int issue_write_reg(const struct sr_dev_inst *sdi,
143 unsigned int reg, unsigned int value)
145 struct dev_context *devc;
146 struct acquisition_state *acq;
149 acq = devc->acquisition;
151 acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_REG);
152 acq->xfer_buf_out[1] = LWLA_WORD(reg);
153 acq->xfer_buf_out[2] = LWLA_WORD_0(value);
154 acq->xfer_buf_out[3] = LWLA_WORD_1(value);
156 acq->xfer_out->length = 4 * sizeof(uint16_t);
158 return submit_transfer(devc, acq->xfer_out);
161 /* Issue a register write command as an asynchronous USB transfer for the
162 * next register/value pair of the currently active register write sequence.
164 static int issue_next_write_reg(const struct sr_dev_inst *sdi)
166 struct dev_context *devc;
167 struct regval_pair *regval;
172 if (devc->reg_write_pos >= devc->reg_write_len) {
173 sr_err("Already written all registers in sequence.");
176 regval = &devc->reg_write_seq[devc->reg_write_pos];
178 ret = issue_write_reg(sdi, regval->reg, regval->val);
182 ++devc->reg_write_pos;
186 /* Issue a capture status request as an asynchronous USB transfer.
188 static void request_capture_status(const struct sr_dev_inst *sdi)
190 struct dev_context *devc;
191 struct acquisition_state *acq;
194 acq = devc->acquisition;
196 acq->xfer_buf_out[0] = LWLA_WORD(CMD_CAP_STATUS);
197 acq->xfer_buf_out[1] = LWLA_WORD(CAP_STAT_ADDR);
198 acq->xfer_buf_out[2] = LWLA_WORD(CAP_STAT_LEN);
200 acq->xfer_out->length = 3 * sizeof(uint16_t);
202 if (submit_transfer(devc, acq->xfer_out) == SR_OK)
203 devc->state = STATE_STATUS_REQUEST;
206 /* Issue a request for the capture buffer fill level as
207 * an asynchronous USB transfer.
209 static void request_capture_length(const struct sr_dev_inst *sdi)
211 struct dev_context *devc;
212 struct acquisition_state *acq;
215 acq = devc->acquisition;
217 acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_REG);
218 acq->xfer_buf_out[1] = LWLA_WORD(REG_MEM_FILL);
220 acq->xfer_out->length = 2 * sizeof(uint16_t);
222 if (submit_transfer(devc, acq->xfer_out) == SR_OK)
223 devc->state = STATE_LENGTH_REQUEST;
226 /* Initiate the capture memory read operation: Reset the acquisition state
227 * and start a sequence of register writes in order to set up the device for
228 * reading from the capture buffer.
230 static void issue_read_start(const struct sr_dev_inst *sdi)
232 struct dev_context *devc;
233 struct acquisition_state *acq;
234 struct regval_pair *regvals;
237 acq = devc->acquisition;
239 /* Reset RLE state. */
240 acq->rle = RLE_STATE_DATA;
244 acq->samples_done = 0;
246 /* For some reason, the start address is 4 rather than 0. */
247 acq->mem_addr_done = 4;
248 acq->mem_addr_next = 4;
249 acq->mem_addr_stop = acq->mem_addr_fill;
251 /* Sample position in the packet output buffer. */
254 regvals = devc->reg_write_seq;
256 regvals[0].reg = REG_DIV_BYPASS;
259 regvals[1].reg = REG_MEM_CTRL2;
262 regvals[2].reg = REG_MEM_CTRL4;
265 devc->reg_write_pos = 0;
266 devc->reg_write_len = 3;
268 if (issue_next_write_reg(sdi) == SR_OK)
269 devc->state = STATE_READ_PREPARE;
272 /* Issue a command as an asynchronous USB transfer which returns the device
273 * to normal state after a read operation. Sets a new device context state
276 static void issue_read_end(const struct sr_dev_inst *sdi)
278 struct dev_context *devc;
282 if (issue_write_reg(sdi, REG_DIV_BYPASS, 0) == SR_OK)
283 devc->state = STATE_READ_END;
286 /* Decode an incoming response to a buffer fill level request and act on it
287 * as appropriate. Note that this function changes the device context state.
289 static void process_capture_length(const struct sr_dev_inst *sdi)
291 struct dev_context *devc;
292 struct acquisition_state *acq;
295 acq = devc->acquisition;
297 if (acq->xfer_in->actual_length != 4) {
298 sr_err("Received size %d doesn't match expected size 4.",
299 acq->xfer_in->actual_length);
300 devc->transfer_error = TRUE;
303 acq->mem_addr_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
305 sr_dbg("%zu words in capture buffer.", acq->mem_addr_fill);
307 if (acq->mem_addr_fill > 0 && sdi->status == SR_ST_ACTIVE)
308 issue_read_start(sdi);
313 /* Initiate a sequence of register write commands with the effect of
314 * cancelling a running capture operation. This sets a new device state
315 * if issuing the first command succeeds.
317 static void issue_stop_capture(const struct sr_dev_inst *sdi)
319 struct dev_context *devc;
320 struct regval_pair *regvals;
324 if (devc->stopping_in_progress)
327 regvals = devc->reg_write_seq;
329 regvals[0].reg = REG_CMD_CTRL2;
332 regvals[1].reg = REG_CMD_CTRL3;
335 regvals[2].reg = REG_CMD_CTRL4;
338 regvals[3].reg = REG_CMD_CTRL1;
341 regvals[4].reg = REG_DIV_BYPASS;
344 devc->reg_write_pos = 0;
345 devc->reg_write_len = 5;
347 if (issue_next_write_reg(sdi) == SR_OK) {
348 devc->stopping_in_progress = TRUE;
349 devc->state = STATE_STOP_CAPTURE;
353 /* Decode an incoming capture status response and act on it as appropriate.
354 * Note that this function changes the device state.
356 static void process_capture_status(const struct sr_dev_inst *sdi)
359 struct dev_context *devc;
360 struct acquisition_state *acq;
361 unsigned int mem_fill;
365 acq = devc->acquisition;
367 if (acq->xfer_in->actual_length != CAP_STAT_LEN * 8) {
368 sr_err("Received size %d doesn't match expected size %d.",
369 acq->xfer_in->actual_length, CAP_STAT_LEN * 8);
370 devc->transfer_error = TRUE;
374 /* TODO: Find out the actual bit width of these fields as stored
375 * in the FPGA. These fields are definitely less than 64 bit wide
376 * internally, and the unused bits occasionally even contain garbage.
378 mem_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
379 duration = LWLA_TO_UINT32(acq->xfer_buf_in[4]);
380 flags = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
382 /* The LWLA1034 runs at 125 MHz if the clock divider is bypassed.
383 * However, the time base used for the duration is apparently not
384 * adjusted for this "boost" mode. Whereas normally the duration
385 * unit is 1 ms, it is 0.8 ms when the clock divider is bypassed.
386 * As 0.8 = 100 MHz / 125 MHz, it seems that the internal cycle
387 * counter period is the same as at the 100 MHz setting.
389 if (acq->bypass_clockdiv)
390 acq->duration_now = duration * 4 / 5;
392 acq->duration_now = duration;
394 sr_spew("Captured %u words, %" PRIu64 " ms, flags 0x%02X.",
395 mem_fill, acq->duration_now, flags);
397 if ((flags & STATUS_TRIGGERED) > (acq->capture_flags & STATUS_TRIGGERED))
398 sr_info("Capture triggered.");
400 acq->capture_flags = flags;
402 if (acq->duration_now >= acq->duration_max) {
403 sr_dbg("Time limit reached, stopping capture.");
404 issue_stop_capture(sdi);
407 devc->state = STATE_STATUS_WAIT;
409 if ((acq->capture_flags & STATUS_TRIGGERED) == 0) {
410 sr_spew("Waiting for trigger.");
411 } else if ((acq->capture_flags & STATUS_MEM_AVAIL) == 0) {
412 sr_dbg("Capture memory filled.");
413 request_capture_length(sdi);
414 } else if ((acq->capture_flags & STATUS_CAPTURING) != 0) {
415 sr_spew("Sampling in progress.");
419 /* Issue a capture buffer read request as an asynchronous USB transfer.
420 * The address and size of the memory area to read are derived from the
421 * current acquisition state.
423 static void request_read_mem(const struct sr_dev_inst *sdi)
425 struct dev_context *devc;
426 struct acquisition_state *acq;
430 acq = devc->acquisition;
432 if (acq->mem_addr_next >= acq->mem_addr_stop)
435 /* Always read a multiple of 8 device words. */
436 count = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8;
437 count = MIN(count, READ_CHUNK_LEN);
439 acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM);
440 acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
441 acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
442 acq->xfer_buf_out[3] = LWLA_WORD_0(count);
443 acq->xfer_buf_out[4] = LWLA_WORD_1(count);
445 acq->xfer_out->length = 5 * sizeof(uint16_t);
447 if (submit_transfer(devc, acq->xfer_out) == SR_OK) {
448 acq->mem_addr_next += count;
449 devc->state = STATE_READ_REQUEST;
453 /* Demangle and decompress incoming sample data from the capture buffer.
454 * The data chunk is taken from the acquisition state, and is expected to
455 * contain a multiple of 8 device words.
456 * All data currently in the acquisition buffer will be processed. Packets
457 * of decoded samples are sent off to the session bus whenever the output
458 * buffer becomes full while decoding.
460 static int process_sample_data(const struct sr_dev_inst *sdi)
463 uint64_t high_nibbles;
465 struct dev_context *devc;
466 struct acquisition_state *acq;
469 struct sr_datafeed_packet packet;
470 struct sr_datafeed_logic logic;
473 size_t out_max_samples;
474 size_t out_run_samples;
476 size_t in_words_left;
480 acq = devc->acquisition;
482 if (acq->mem_addr_done >= acq->mem_addr_stop
483 || acq->samples_done >= acq->samples_max)
486 in_words_left = MIN(acq->mem_addr_stop - acq->mem_addr_done,
488 expect_len = LWLA1034_MEMBUF_LEN(in_words_left) * sizeof(uint32_t);
489 actual_len = acq->xfer_in->actual_length;
491 if (actual_len != expect_len) {
492 sr_err("Received size %zu does not match expected size %zu.",
493 actual_len, expect_len);
494 devc->transfer_error = TRUE;
497 acq->mem_addr_done += in_words_left;
499 /* Prepare session packet. */
500 packet.type = SR_DF_LOGIC;
501 packet.payload = &logic;
502 logic.unitsize = UNIT_SIZE;
503 logic.data = acq->out_packet;
505 slice = acq->xfer_buf_in;
506 si = 0; /* word index within slice */
509 /* Calculate number of samples to write into packet. */
510 out_max_samples = MIN(acq->samples_max - acq->samples_done,
511 PACKET_LENGTH - acq->out_index);
512 out_run_samples = MIN(acq->run_len, out_max_samples);
514 /* Expand run-length samples into session packet. */
515 sample = acq->sample;
516 out_p = &acq->out_packet[acq->out_index * UNIT_SIZE];
518 for (ri = 0; ri < out_run_samples; ++ri) {
519 out_p[0] = sample & 0xFF;
520 out_p[1] = (sample >> 8) & 0xFF;
521 out_p[2] = (sample >> 16) & 0xFF;
522 out_p[3] = (sample >> 24) & 0xFF;
523 out_p[4] = (sample >> 32) & 0xFF;
526 acq->run_len -= out_run_samples;
527 acq->out_index += out_run_samples;
528 acq->samples_done += out_run_samples;
530 /* Packet full or sample count limit reached? */
531 if (out_run_samples == out_max_samples) {
532 logic.length = acq->out_index * UNIT_SIZE;
533 sr_session_send(sdi, &packet);
536 if (acq->samples_done >= acq->samples_max)
537 return SR_OK; /* sample limit reached */
538 if (acq->run_len > 0)
539 continue; /* need another packet */
542 if (in_words_left == 0)
543 break; /* done with current chunk */
545 /* Now work on the current slice. */
546 high_nibbles = LWLA_TO_UINT32(slice[8]);
547 word = LWLA_TO_UINT32(slice[si]);
548 word |= (high_nibbles << (4 * si + 4)) & ((uint64_t)0xF << 32);
550 if (acq->rle == RLE_STATE_DATA) {
551 acq->sample = word & ALL_CHANNELS_MASK;
552 acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1;
553 if (word & RLE_FLAG_LEN_FOLLOWS)
554 acq->rle = RLE_STATE_LEN;
556 acq->run_len += word << 1;
557 acq->rle = RLE_STATE_DATA;
560 /* Move to next word. */
567 /* Send out partially filled packet if this was the last chunk. */
568 if (acq->mem_addr_done >= acq->mem_addr_stop && acq->out_index > 0) {
569 logic.length = acq->out_index * UNIT_SIZE;
570 sr_session_send(sdi, &packet);
576 /* Finish an acquisition session. This sends the end packet to the session
577 * bus and removes the listener for asynchronous USB transfers.
579 static void end_acquisition(struct sr_dev_inst *sdi)
581 struct drv_context *drvc;
582 struct dev_context *devc;
583 struct sr_datafeed_packet packet;
585 drvc = sdi->driver->priv;
588 if (devc->state == STATE_IDLE)
591 devc->state = STATE_IDLE;
593 /* Remove USB file descriptors from polling. */
594 usb_source_remove(sdi->session, drvc->sr_ctx);
596 packet.type = SR_DF_END;
597 sr_session_send(sdi, &packet);
599 lwla_free_acquisition_state(devc->acquisition);
600 devc->acquisition = NULL;
602 sdi->status = SR_ST_ACTIVE;
605 /* USB output transfer completion callback.
607 static void receive_transfer_out(struct libusb_transfer *transfer)
609 struct sr_dev_inst *sdi;
610 struct dev_context *devc;
612 sdi = transfer->user_data;
615 if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
616 sr_err("Transfer to device failed: %d.", transfer->status);
617 devc->transfer_error = TRUE;
621 if (devc->reg_write_pos < devc->reg_write_len) {
622 issue_next_write_reg(sdi);
624 switch (devc->state) {
625 case STATE_START_CAPTURE:
626 devc->state = STATE_STATUS_WAIT;
628 case STATE_STATUS_REQUEST:
629 devc->state = STATE_STATUS_RESPONSE;
630 submit_transfer(devc, devc->acquisition->xfer_in);
632 case STATE_STOP_CAPTURE:
633 if (sdi->status == SR_ST_ACTIVE)
634 request_capture_length(sdi);
636 end_acquisition(sdi);
638 case STATE_LENGTH_REQUEST:
639 devc->state = STATE_LENGTH_RESPONSE;
640 submit_transfer(devc, devc->acquisition->xfer_in);
642 case STATE_READ_PREPARE:
643 request_read_mem(sdi);
645 case STATE_READ_REQUEST:
646 devc->state = STATE_READ_RESPONSE;
647 submit_transfer(devc, devc->acquisition->xfer_in);
650 end_acquisition(sdi);
653 sr_err("Unexpected device state %d.", devc->state);
659 /* USB input transfer completion callback.
661 static void receive_transfer_in(struct libusb_transfer *transfer)
663 struct sr_dev_inst *sdi;
664 struct dev_context *devc;
665 struct acquisition_state *acq;
667 sdi = transfer->user_data;
669 acq = devc->acquisition;
671 if (transfer->status != LIBUSB_TRANSFER_COMPLETED) {
672 sr_err("Transfer from device failed: %d.", transfer->status);
673 devc->transfer_error = TRUE;
677 switch (devc->state) {
678 case STATE_STATUS_RESPONSE:
679 process_capture_status(sdi);
681 case STATE_LENGTH_RESPONSE:
682 process_capture_length(sdi);
684 case STATE_READ_RESPONSE:
685 if (process_sample_data(sdi) == SR_OK
686 && acq->mem_addr_next < acq->mem_addr_stop
687 && acq->samples_done < acq->samples_max)
688 request_read_mem(sdi);
693 sr_err("Unexpected device state %d.", devc->state);
698 /* Initialize the LWLA. This downloads a bitstream into the FPGA
699 * and executes a simple device test sequence.
701 SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
703 struct dev_context *devc;
709 /* Force reload of bitstream */
710 devc->cur_clock_config = CONF_CLOCK_NONE;
712 ret = lwla_set_clock_config(sdi);
717 ret = lwla_write_reg(sdi->conn, REG_CMD_CTRL2, 100);
721 ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL1, &value);
724 sr_dbg("Received test word 0x%08X back.", value);
725 if (value != 0x12345678)
728 ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL4, &value);
731 sr_dbg("Received test word 0x%08X back.", value);
732 if (value != 0x12345678)
735 ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL3, &value);
738 sr_dbg("Received test word 0x%08X back.", value);
739 if (value != 0x87654321)
745 SR_PRIV int lwla_convert_trigger(const struct sr_dev_inst *sdi)
747 struct dev_context *devc;
748 struct sr_trigger *trigger;
749 struct sr_trigger_stage *stage;
750 struct sr_trigger_match *match;
752 uint64_t channel_index;
756 devc->trigger_mask = 0;
757 devc->trigger_values = 0;
758 devc->trigger_edge_mask = 0;
760 if (!(trigger = sr_session_trigger_get(sdi->session)))
763 if (g_slist_length(trigger->stages) > 1) {
764 sr_err("This device only supports 1 trigger stage.");
768 for (l = trigger->stages; l; l = l->next) {
770 for (m = stage->matches; m; m = m->next) {
772 if (!match->channel->enabled)
773 /* Ignore disabled channels with a trigger. */
775 channel_index = (uint64_t)1 << match->channel->index;
776 devc->trigger_mask |= channel_index;
777 switch (match->match) {
779 devc->trigger_values |= channel_index;
781 case SR_TRIGGER_RISING:
782 devc->trigger_values |= channel_index;
783 /* Fall through for edge mask. */
784 case SR_TRIGGER_FALLING:
785 devc->trigger_edge_mask |= channel_index;
794 /* Select the LWLA clock configuration. If the clock source changed from
795 * the previous setting, this will download a new bitstream to the FPGA.
797 SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi)
799 struct dev_context *devc;
801 enum clock_config choice;
805 if (sdi->status == SR_ST_INACTIVE)
806 choice = CONF_CLOCK_NONE;
807 else if (devc->cfg_clock_source == CLOCK_INTERNAL)
808 choice = CONF_CLOCK_INT;
809 else if (devc->cfg_clock_edge == EDGE_POSITIVE)
810 choice = CONF_CLOCK_EXT_RISE;
812 choice = CONF_CLOCK_EXT_FALL;
814 if (choice != devc->cur_clock_config) {
815 devc->cur_clock_config = CONF_CLOCK_NONE;
816 ret = lwla_send_bitstream(sdi->conn, bitstream_map[choice]);
818 devc->cur_clock_config = choice;
824 /* Configure the LWLA in preparation for an acquisition session.
826 SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi)
828 struct dev_context *devc;
829 struct sr_usb_dev_inst *usb;
830 struct acquisition_state *acq;
831 struct regval_pair regvals[7];
836 acq = devc->acquisition;
838 if (devc->limit_msec > 0) {
839 acq->duration_max = devc->limit_msec;
840 sr_info("Acquisition time limit %" PRIu64 " ms.",
843 acq->duration_max = MAX_LIMIT_MSEC;
845 if (devc->limit_samples > 0) {
846 acq->samples_max = devc->limit_samples;
847 sr_info("Acquisition sample count limit %" PRIu64 ".",
848 devc->limit_samples);
850 acq->samples_max = MAX_LIMIT_SAMPLES;
852 if (devc->cfg_clock_source == CLOCK_INTERNAL) {
853 sr_info("Internal clock, samplerate %" PRIu64 ".",
855 if (devc->samplerate == 0)
857 /* At 125 MHz, the clock divider is bypassed. */
858 acq->bypass_clockdiv = (devc->samplerate > SR_MHZ(100));
860 /* If only one of the limits is set, derive the other one. */
861 if (devc->limit_msec == 0 && devc->limit_samples > 0)
862 acq->duration_max = devc->limit_samples
863 * 1000 / devc->samplerate + 1;
864 else if (devc->limit_samples == 0 && devc->limit_msec > 0)
865 acq->samples_max = devc->limit_msec
866 * devc->samplerate / 1000;
868 acq->bypass_clockdiv = TRUE;
870 if (devc->cfg_clock_edge == EDGE_NEGATIVE)
871 sr_info("External clock, falling edge.");
873 sr_info("External clock, rising edge.");
876 regvals[0].reg = REG_MEM_CTRL2;
879 regvals[1].reg = REG_MEM_CTRL2;
882 regvals[2].reg = REG_CMD_CTRL2;
885 regvals[3].reg = REG_CMD_CTRL3;
886 regvals[3].val = 0x74;
888 regvals[4].reg = REG_CMD_CTRL4;
891 regvals[5].reg = REG_CMD_CTRL1;
894 regvals[6].reg = REG_DIV_BYPASS;
895 regvals[6].val = acq->bypass_clockdiv;
897 ret = lwla_write_regs(usb, regvals, ARRAY_SIZE(regvals));
901 return capture_setup(sdi);
904 /* Start the capture operation on the LWLA device. Beginning with this
905 * function, all USB transfers will be asynchronous until the end of the
906 * acquisition session.
908 SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi)
910 struct dev_context *devc;
911 struct sr_usb_dev_inst *usb;
912 struct acquisition_state *acq;
913 struct regval_pair *regvals;
917 acq = devc->acquisition;
919 acq->duration_now = 0;
920 acq->mem_addr_fill = 0;
921 acq->capture_flags = 0;
923 libusb_fill_bulk_transfer(acq->xfer_out, usb->devhdl, EP_COMMAND,
924 (unsigned char *)acq->xfer_buf_out, 0,
925 &receive_transfer_out,
926 (struct sr_dev_inst *)sdi, USB_TIMEOUT_MS);
928 libusb_fill_bulk_transfer(acq->xfer_in, usb->devhdl, EP_REPLY,
929 (unsigned char *)acq->xfer_buf_in,
930 sizeof acq->xfer_buf_in,
931 &receive_transfer_in,
932 (struct sr_dev_inst *)sdi, USB_TIMEOUT_MS);
934 regvals = devc->reg_write_seq;
936 regvals[0].reg = REG_CMD_CTRL2;
939 regvals[1].reg = REG_CMD_CTRL3;
942 regvals[2].reg = REG_CMD_CTRL4;
945 regvals[3].reg = REG_CMD_CTRL1;
948 devc->reg_write_pos = 0;
949 devc->reg_write_len = 4;
951 devc->state = STATE_START_CAPTURE;
953 return issue_next_write_reg(sdi);
956 /* Allocate an acquisition state object.
958 SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void)
960 struct acquisition_state *acq;
962 acq = g_malloc0(sizeof(struct acquisition_state));
964 acq->xfer_in = libusb_alloc_transfer(0);
966 sr_err("Transfer malloc failed.");
971 acq->xfer_out = libusb_alloc_transfer(0);
972 if (!acq->xfer_out) {
973 sr_err("Transfer malloc failed.");
974 libusb_free_transfer(acq->xfer_in);
982 /* Deallocate an acquisition state object.
984 SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq)
987 libusb_free_transfer(acq->xfer_out);
988 libusb_free_transfer(acq->xfer_in);
993 /* USB I/O source callback.
995 SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data)
997 struct sr_dev_inst *sdi;
998 struct dev_context *devc;
999 struct drv_context *drvc;
1007 drvc = sdi->driver->priv;
1012 /* No timeout: return immediately. */
1016 ret = libusb_handle_events_timeout_completed(drvc->sr_ctx->libusb_ctx,
1019 sr_err("Event handling failed: %s.", libusb_error_name(ret));
1021 /* If no event flags are set the timeout must have expired. */
1022 if (revents == 0 && devc->state == STATE_STATUS_WAIT) {
1023 if (sdi->status == SR_ST_STOPPING)
1024 issue_stop_capture(sdi);
1026 request_capture_status(sdi);
1029 /* Check if an error occurred on a transfer. */
1030 if (devc->transfer_error)
1031 end_acquisition(sdi);