2 * This file is part of the libsigrok project.
4 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #include <glib/gstdio.h>
29 #include "libsigrok.h"
30 #include "libsigrok-internal.h"
33 #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream"
34 #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream"
36 #define MAX_SAMPLE_RATE SR_MHZ(100)
37 #define MAX_4CH_SAMPLE_RATE SR_MHZ(50)
38 #define MAX_7CH_SAMPLE_RATE SR_MHZ(40)
39 #define MAX_8CH_SAMPLE_RATE SR_MHZ(32)
40 #define MAX_10CH_SAMPLE_RATE SR_MHZ(25)
41 #define MAX_13CH_SAMPLE_RATE SR_MHZ(16)
43 #define BASE_CLOCK_0_FREQ SR_MHZ(100)
44 #define BASE_CLOCK_1_FREQ SR_MHZ(160)
46 #define COMMAND_START_ACQUISITION 1
47 #define COMMAND_ABORT_ACQUISITION_ASYNC 2
48 #define COMMAND_WRITE_EEPROM 6
49 #define COMMAND_READ_EEPROM 7
50 #define COMMAND_WRITE_LED_TABLE 0x7a
51 #define COMMAND_SET_LED_MODE 0x7b
52 #define COMMAND_RETURN_TO_BOOTLOADER 0x7c
53 #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d
54 #define COMMAND_FPGA_UPLOAD_INIT 0x7e
55 #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f
56 #define COMMAND_FPGA_WRITE_REGISTER 0x80
57 #define COMMAND_FPGA_READ_REGISTER 0x81
58 #define COMMAND_GET_REVID 0x82
60 #define WRITE_EEPROM_COOKIE1 0x42
61 #define WRITE_EEPROM_COOKIE2 0x55
62 #define READ_EEPROM_COOKIE1 0x33
63 #define READ_EEPROM_COOKIE2 0x81
64 #define ABORT_ACQUISITION_SYNC_PATTERN 0x55
66 #define MAX_EMPTY_TRANSFERS 64
68 static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
70 uint8_t state1 = 0x9b, state2 = 0x54;
74 for (i = 0; i < cnt; i++) {
76 t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39;
77 t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45;
83 static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt)
85 uint8_t state1 = 0x9b, state2 = 0x54;
89 for (i = 0; i < cnt; i++) {
91 t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1;
92 t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2;
98 static int do_ep1_command(const struct sr_dev_inst *sdi,
99 const uint8_t *command, uint8_t cmd_len,
100 uint8_t *reply, uint8_t reply_len)
103 struct sr_usb_dev_inst *usb;
108 if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 ||
109 !command || (reply_len > 0 && !reply))
112 encrypt(buf, command, cmd_len);
114 ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000);
116 sr_dbg("Failed to send EP1 command 0x%02x: %s.",
117 command[0], libusb_error_name(ret));
120 if (xfer != cmd_len) {
121 sr_dbg("Failed to send EP1 command 0x%02x: incorrect length "
122 "%d != %d.", xfer, cmd_len);
129 ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len,
132 sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.",
133 command[0], libusb_error_name(ret));
136 if (xfer != reply_len) {
137 sr_dbg("Failed to receive reply to EP1 command 0x%02x: "
138 "incorrect length %d != %d.", xfer, reply_len);
142 decrypt(reply, buf, reply_len);
147 static int read_eeprom(const struct sr_dev_inst *sdi,
148 uint8_t address, uint8_t length, uint8_t *buf)
150 uint8_t command[5] = {
158 return do_ep1_command(sdi, command, 5, buf, length);
161 static int upload_led_table(const struct sr_dev_inst *sdi,
162 const uint8_t *table, uint8_t offset, uint8_t cnt)
164 uint8_t chunk, command[64];
167 if (cnt < 1 || cnt + offset > 64 || !table)
171 chunk = (cnt > 32 ? 32 : cnt);
173 command[0] = COMMAND_WRITE_LED_TABLE;
176 memcpy(command + 3, table, chunk);
178 ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0);
190 static int set_led_mode(const struct sr_dev_inst *sdi,
191 uint8_t animate, uint16_t t2reload, uint8_t div,
194 uint8_t command[6] = {
195 COMMAND_SET_LED_MODE,
203 return do_ep1_command(sdi, command, 6, NULL, 0);
206 static int read_fpga_register(const struct sr_dev_inst *sdi,
207 uint8_t address, uint8_t *value)
209 uint8_t command[3] = {
210 COMMAND_FPGA_READ_REGISTER,
215 return do_ep1_command(sdi, command, 3, value, 1);
218 static int write_fpga_registers(const struct sr_dev_inst *sdi,
219 uint8_t (*regs)[2], uint8_t cnt)
224 if (cnt < 1 || cnt > 31)
227 command[0] = COMMAND_FPGA_WRITE_REGISTER;
229 for (i = 0; i < cnt; i++) {
230 command[2 + 2 * i] = regs[i][0];
231 command[3 + 2 * i] = regs[i][1];
234 return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0);
237 static int write_fpga_register(const struct sr_dev_inst *sdi,
238 uint8_t address, uint8_t value)
240 uint8_t regs[2] = { address, value };
242 return write_fpga_registers(sdi, ®s, 1);
245 static uint8_t map_eeprom_data(uint8_t v)
247 return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69;
250 static int prime_fpga(const struct sr_dev_inst *sdi)
252 uint8_t eeprom_data[16];
253 uint8_t old_reg_10, version;
254 uint8_t regs[8][2] = {
266 if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK)
269 if ((ret = read_fpga_register(sdi, 10, &old_reg_10)) != SR_OK)
272 regs[0][1] = (old_reg_10 &= 0x7f);
273 regs[1][1] |= old_reg_10;
274 regs[3][1] |= old_reg_10;
275 regs[4][1] |= old_reg_10;
277 for (i = 0; i < 16; i++) {
278 regs[2][1] = eeprom_data[i];
279 regs[5][1] = map_eeprom_data(eeprom_data[i]);
281 ret = write_fpga_registers(sdi, ®s[2], 6);
283 ret = write_fpga_registers(sdi, ®s[0], 8);
288 if ((ret = write_fpga_register(sdi, 10, old_reg_10)) != SR_OK)
291 if ((ret = read_fpga_register(sdi, 0, &version)) != SR_OK)
294 if (version != 0x10 && version != 0x40 && version != 0x41) {
295 sr_err("Unsupported FPGA version: 0x%02x.", version);
302 static void make_heartbeat(uint8_t *table, int len)
306 memset(table, 0, len);
308 for (i = 0; i < 2; i++)
309 for (j = 0; j < len; j++)
310 *table++ = sin(j * M_PI / len) * 255;
313 static int configure_led(const struct sr_dev_inst *sdi)
318 make_heartbeat(table, 64);
319 if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK)
322 return set_led_mode(sdi, 1, 6250, 0, 1);
325 static int upload_fpga_bitstream(const struct sr_dev_inst *sdi,
326 enum voltage_range vrange)
328 struct dev_context *devc;
329 int offset, chunksize, ret;
330 const char *filename;
331 uint8_t len, buf[256 * 62], command[64];
336 if (devc->cur_voltage_range == vrange)
339 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) {
341 case VOLTAGE_RANGE_18_33_V:
342 filename = FPGA_FIRMWARE_18;
344 case VOLTAGE_RANGE_5_V:
345 filename = FPGA_FIRMWARE_33;
348 sr_err("Unsupported voltage range.");
352 sr_info("Uploading FPGA bitstream at %s.", filename);
353 if (!(fw = g_fopen(filename, "rb"))) {
354 sr_err("Unable to open bitstream file %s for reading: %s.",
355 filename, strerror(errno));
359 buf[0] = COMMAND_FPGA_UPLOAD_INIT;
360 if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) {
366 chunksize = fread(buf, 1, sizeof(buf), fw);
370 for (offset = 0; offset < chunksize; offset += 62) {
371 len = (offset + 62 > chunksize ?
372 chunksize - offset : 62);
373 command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA;
375 memcpy(command + 2, buf + offset, len);
376 ret = do_ep1_command(sdi, command, len + 2, NULL, 0);
383 sr_info("Uploaded %d bytes.", chunksize);
386 sr_info("FPGA bitstream upload done.");
389 if ((ret = prime_fpga(sdi)) != SR_OK)
392 if ((ret = configure_led(sdi)) != SR_OK)
395 devc->cur_voltage_range = vrange;
399 static int abort_acquisition_sync(const struct sr_dev_inst *sdi)
401 static const uint8_t command[2] = {
402 COMMAND_ABORT_ACQUISITION_SYNC,
403 ABORT_ACQUISITION_SYNC_PATTERN,
405 uint8_t reply, expected_reply;
408 if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK)
411 expected_reply = ~command[1];
412 if (reply != expected_reply) {
413 sr_err("Invalid response for abort acquisition command: "
414 "0x%02x != 0x%02x.", reply, expected_reply);
421 SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
422 uint64_t samplerate, uint16_t channels)
424 uint8_t clock_select, reg1, reg10;
426 int i, ret, nchan = 0;
427 struct dev_context *devc;
431 if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) {
432 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
436 if (BASE_CLOCK_0_FREQ % samplerate == 0 &&
437 (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) {
439 } else if (BASE_CLOCK_1_FREQ % samplerate == 0 &&
440 (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) {
443 sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate);
447 for (i = 0; i < 16; i++)
448 if (channels & (1U << i))
451 if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) ||
452 (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) ||
453 (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) ||
454 (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) ||
455 (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) {
456 sr_err("Unable to sample at %" PRIu64 "Hz "
457 "with this many channels.", samplerate);
461 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
465 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
468 /* Ignore FIFO overflow on previous capture */
471 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x08) {
472 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x08. "
473 "Proceeding anyway.", reg1);
476 if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
479 if ((ret = write_fpga_register(sdi, 10, clock_select)) != SR_OK)
482 if ((ret = write_fpga_register(sdi, 4, (uint8_t)(div - 1))) != SR_OK)
485 if ((ret = write_fpga_register(sdi, 2, (uint8_t)(channels & 0xff))) != SR_OK)
488 if ((ret = write_fpga_register(sdi, 3, (uint8_t)(channels >> 8))) != SR_OK)
491 if ((ret = write_fpga_register(sdi, 1, 0x42)) != SR_OK)
494 if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK)
497 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
500 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) {
501 sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x48. "
502 "Proceeding anyway.", reg1);
505 if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK)
508 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) {
509 sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. "
510 "Proceeding anyway.", reg10, clock_select);
516 SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi)
518 static const uint8_t command[1] = {
519 COMMAND_START_ACQUISITION,
523 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
526 return write_fpga_register(sdi, 1, 0x41);
529 SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi)
531 static const uint8_t command[1] = {
532 COMMAND_ABORT_ACQUISITION_ASYNC,
535 uint8_t reg1, reg8, reg9;
536 struct dev_context *devc;
540 if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK)
543 if ((ret = write_fpga_register(sdi, 1, 0x00)) != SR_OK)
546 if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK)
549 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && (reg1 & ~0x20) != 0x08) {
550 sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08.", reg1 & ~0x20);
554 if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK)
557 if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK)
560 if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 & 0x20) {
561 sr_warn("FIFO overflow, capture data may be truncated.");
568 SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi)
571 struct dev_context *devc;
576 devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN;
578 if ((ret = abort_acquisition_sync(sdi)) != SR_OK)
581 if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK)
584 /* mcupro Saleae16 has firmware pre-stored in FPGA.
585 So, we can query it right away. */
586 if (read_fpga_register(sdi, 0, &version) == SR_OK &&
587 (version == 0x40 || version == 0x41)) {
588 sr_info("mcupro Saleae16 detected.");
589 devc->fpga_variant = FPGA_VARIANT_MCUPRO;
591 sr_info("Original Saleae Logic16 detected.");
592 devc->fpga_variant = FPGA_VARIANT_ORIGINAL;
595 ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range);
602 static void finish_acquisition(struct sr_dev_inst *sdi)
604 struct sr_datafeed_packet packet;
605 struct dev_context *devc;
609 /* Terminate session. */
610 packet.type = SR_DF_END;
611 sr_session_send(devc->cb_data, &packet);
613 /* Remove fds from polling. */
614 usb_source_remove(sdi->session, devc->ctx);
616 devc->num_transfers = 0;
617 g_free(devc->transfers);
618 g_free(devc->convbuffer);
620 soft_trigger_logic_free(devc->stl);
625 static void free_transfer(struct libusb_transfer *transfer)
627 struct sr_dev_inst *sdi;
628 struct dev_context *devc;
631 sdi = transfer->user_data;
634 g_free(transfer->buffer);
635 transfer->buffer = NULL;
636 libusb_free_transfer(transfer);
638 for (i = 0; i < devc->num_transfers; i++) {
639 if (devc->transfers[i] == transfer) {
640 devc->transfers[i] = NULL;
645 devc->submitted_transfers--;
646 if (devc->submitted_transfers == 0)
647 finish_acquisition(sdi);
650 static void resubmit_transfer(struct libusb_transfer *transfer)
654 if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS)
657 free_transfer(transfer);
658 /* TODO: Stop session? */
660 sr_err("%s: %s", __func__, libusb_error_name(ret));
663 static size_t convert_sample_data(struct dev_context *devc,
664 uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt)
666 uint16_t *channel_data;
669 uint16_t sample, channel_mask;
673 channel_data = devc->channel_data;
674 cur_channel = devc->cur_channel;
677 sample = src[0] | (src[1] << 8);
680 channel_mask = devc->channel_masks[cur_channel];
682 for (i = 15; i >= 0; --i, sample >>= 1)
684 channel_data[i] |= channel_mask;
686 if (++cur_channel == devc->num_channels) {
688 if (destcnt < 16 * 2) {
689 sr_err("Conversion buffer too small!");
692 memcpy(dest, channel_data, 16 * 2);
693 memset(channel_data, 0, 16 * 2);
700 devc->cur_channel = cur_channel;
705 SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer)
707 gboolean packet_has_error = FALSE;
708 struct sr_datafeed_packet packet;
709 struct sr_datafeed_logic logic;
710 struct sr_dev_inst *sdi;
711 struct dev_context *devc;
712 size_t new_samples, num_samples;
714 int pre_trigger_samples;
716 sdi = transfer->user_data;
720 * If acquisition has already ended, just free any queued up
721 * transfer that come in.
723 if (devc->sent_samples < 0) {
724 free_transfer(transfer);
728 sr_info("receive_transfer(): status %s received %d bytes.",
729 libusb_error_name(transfer->status), transfer->actual_length);
731 switch (transfer->status) {
732 case LIBUSB_TRANSFER_NO_DEVICE:
733 devc->sent_samples = -2;
734 free_transfer(transfer);
736 case LIBUSB_TRANSFER_COMPLETED:
737 case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */
740 packet_has_error = TRUE;
744 if (transfer->actual_length & 1) {
745 sr_err("Got an odd number of bytes from the device. "
746 "This should not happen.");
747 /* Bail out right away. */
748 packet_has_error = TRUE;
749 devc->empty_transfer_count = MAX_EMPTY_TRANSFERS;
752 if (transfer->actual_length == 0 || packet_has_error) {
753 devc->empty_transfer_count++;
754 if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) {
756 * The FX2 gave up. End the acquisition, the frontend
757 * will work out that the samplecount is short.
759 devc->sent_samples = -2;
760 free_transfer(transfer);
762 resubmit_transfer(transfer);
766 devc->empty_transfer_count = 0;
769 new_samples = convert_sample_data(devc, devc->convbuffer,
770 devc->convbuffer_size, transfer->buffer, transfer->actual_length);
772 if (new_samples > 0) {
773 if (devc->trigger_fired) {
774 /* Send the incoming transfer to the session bus. */
775 packet.type = SR_DF_LOGIC;
776 packet.payload = &logic;
777 if (devc->limit_samples &&
778 new_samples > devc->limit_samples - devc->sent_samples)
779 new_samples = devc->limit_samples - devc->sent_samples;
780 logic.length = new_samples * 2;
782 logic.data = devc->convbuffer;
783 sr_session_send(devc->cb_data, &packet);
784 devc->sent_samples += new_samples;
786 trigger_offset = soft_trigger_logic_check(devc->stl,
787 devc->convbuffer, new_samples * 2, &pre_trigger_samples);
788 if (trigger_offset > -1) {
789 devc->sent_samples += pre_trigger_samples;
790 packet.type = SR_DF_LOGIC;
791 packet.payload = &logic;
792 num_samples = new_samples - trigger_offset;
793 if (devc->limit_samples &&
794 num_samples > devc->limit_samples - devc->sent_samples)
795 num_samples = devc->limit_samples - devc->sent_samples;
796 logic.length = num_samples * 2;
798 logic.data = devc->convbuffer + trigger_offset * 2;
799 sr_session_send(devc->cb_data, &packet);
800 devc->sent_samples += num_samples;
802 devc->trigger_fired = TRUE;
806 if (devc->limit_samples &&
807 (uint64_t)devc->sent_samples >= devc->limit_samples) {
808 devc->sent_samples = -2;
809 free_transfer(transfer);
814 resubmit_transfer(transfer);