hardware/rigol-ds/protocol.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
   5  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   6  * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 3 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdlib.h>
  23 #include <stdarg.h>
  24 #include <unistd.h>
  25 #include <errno.h>
  26 #include <string.h>
  27 #include <math.h>
  28 #include <ctype.h>
  29 #include <time.h>
  30 #include <glib.h>
  31 #include "libsigrok.h"
  32 #include "libsigrok-internal.h"
  33 #include "protocol.h"
  34
  35 /*
  36  * This is a unified protocol driver for the DS1000 and DS2000 series.
  37  *
  38  * DS1000 support tested with a Rigol DS1102D.
  39  *
  40  * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02.
  41  *
  42  * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think)
  43  * standard. If you want to read it - it costs real money...
  44  *
  45  * Every response from the scope has a linefeed appended because the
  46  * standard says so. In principle this could be ignored because sending the
  47  * next command clears the output queue of the scope. This driver tries to
  48  * avoid doing that because it may cause an error being generated inside the
  49  * scope and who knows what bugs the firmware has WRT this.
  50  *
  51  * Waveform data is transferred in a format called "arbitrary block program
  52  * data" specified in IEEE 488.2. See Agilents programming manuals for their
  53  * 2000/3000 series scopes for a nice description.
  54  *
  55  * Each data block from the scope has a header, e.g. "#900000001400".
  56  * The '#' marks the start of a block.
  57  * Next is one ASCII decimal digit between 1 and 9, this gives the number of
  58  * ASCII decimal digits following.
  59  * Last are the ASCII decimal digits giving the number of bytes (not
  60  * samples!) in the block.
  61  *
  62  * After this header as many data bytes as indicated follow.
  63  *
  64  * Each data block has a trailing linefeed too.
  65  */
  66
  67 static int parse_int(const char *str, int *ret)
  68 {
  69         char *e;
  70         long tmp;
  71
  72         errno = 0;
  73         tmp = strtol(str, &e, 10);
  74         if (e == str || *e != '\0') {
  75                 sr_dbg("Failed to parse integer: '%s'", str);
  76                 return SR_ERR;
  77         }
  78         if (errno) {
  79                 sr_dbg("Failed to parse integer: '%s', numerical overflow", str);
  80                 return SR_ERR;
  81         }
  82         if (tmp > INT_MAX || tmp < INT_MIN) {
  83                 sr_dbg("Failed to parse integer: '%s', value to large/small", str);
  84                 return SR_ERR;
  85         }
  86
  87         *ret = (int)tmp;
  88         return SR_OK;
  89 }
  90
  91 /* Set the next event to wait for in rigol_ds_receive */
  92 static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event)
  93 {
  94         if (event == WAIT_STOP)
  95                 devc->wait_status = 2;
  96         else
  97                 devc->wait_status = 1;
  98         devc->wait_event = event;
  99 }
 100
 101 /*
 102  * Waiting for a event will return a timeout after 2 to 3 seconds in order
 103  * to not block the application.
 104  */
 105 static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2)
 106 {
 107         char *buf;
 108         struct dev_context *devc;
 109         time_t start;
 110
 111         if (!(devc = sdi->priv))
 112                 return SR_ERR;
 113
 114         start = time(NULL);
 115
 116         /*
 117          * Trigger status may return:
 118          * "TD" or "T'D" - triggered
 119          * "AUTO"        - autotriggered
 120          * "RUN"         - running
 121          * "WAIT"        - waiting for trigger
 122          * "STOP"        - stopped
 123          */
 124
 125         if (devc->wait_status == 1) {
 126                 do {
 127                         if (time(NULL) - start >= 3) {
 128                                 sr_dbg("Timeout waiting for trigger");
 129                                 return SR_ERR_TIMEOUT;
 130                         }
 131
 132                         if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
 133                                 return SR_ERR;
 134                 } while (buf[0] == status1 || buf[0] == status2);
 135
 136                 devc->wait_status = 2;
 137         }
 138         if (devc->wait_status == 2) {
 139                 do {
 140                         if (time(NULL) - start >= 3) {
 141                                 sr_dbg("Timeout waiting for trigger");
 142                                 return SR_ERR_TIMEOUT;
 143                         }
 144
 145                         if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
 146                                 return SR_ERR;
 147                 } while (buf[0] != status1 && buf[0] != status2);
 148
 149                 rigol_ds_set_wait_event(devc, WAIT_NONE);
 150         }
 151
 152         return SR_OK;
 153 }
 154
 155 /*
 156  * For live capture we need to wait for a new trigger event to ensure that
 157  * sample data is not returned twice.
 158  *
 159  * Unfortunately this will never really work because for sufficiently fast
 160  * timebases and trigger rates it just can't catch the status changes.
 161  *
 162  * What would be needed is a trigger event register with autoreset like the
 163  * Agilents have. The Rigols don't seem to have anything like this.
 164  *
 165  * The workaround is to only wait for the trigger when the timebase is slow
 166  * enough. Of course this means that for faster timebases sample data can be
 167  * returned multiple times, this effect is mitigated somewhat by sleeping
 168  * for about one sweep time in that case.
 169  */
 170 static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi)
 171 {
 172         struct dev_context *devc;
 173         long s;
 174
 175         if (!(devc = sdi->priv))
 176                 return SR_ERR;
 177
 178         /*
 179          * If timebase < 50 msecs/DIV just sleep about one sweep time except
 180          * for really fast sweeps.
 181          */
 182         if (devc->timebase < 0.0499) {
 183                 if (devc->timebase > 0.99e-6) {
 184                         /*
 185                          * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100
 186                          * -> 85 percent of sweep time
 187                          */
 188                         s = (devc->timebase * devc->model->num_horizontal_divs
 189                              * 85e6) / 100L;
 190                         sr_spew("Sleeping for %ld usecs instead of trigger-wait", s);
 191                         g_usleep(s);
 192                 }
 193                 rigol_ds_set_wait_event(devc, WAIT_NONE);
 194                 return SR_OK;
 195         } else {
 196                 return rigol_ds_event_wait(sdi, 'T', 'A');
 197         }
 198 }
 199
 200 /* Wait for scope to got to "Stop" in single shot mode */
 201 static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi)
 202 {
 203         return rigol_ds_event_wait(sdi, 'S', 'S');
 204 }
 205
 206 /* Check that a single shot acquisition actually succeeded on the DS2000 */
 207 static int rigol_ds_check_stop(const struct sr_dev_inst *sdi)
 208 {
 209         struct dev_context *devc;
 210         struct sr_probe *probe;
 211         int tmp;
 212
 213         if (!(devc = sdi->priv))
 214                 return SR_ERR;
 215
 216         probe = devc->channel_entry->data;
 217
 218         if (sr_scpi_send(sdi->conn, ":WAV:SOUR CHAN%d",
 219                           probe->index + 1) != SR_OK)
 220                 return SR_ERR;
 221         /* Check that the number of samples will be accepted */
 222         if (sr_scpi_send(sdi->conn, ":WAV:POIN %d;*OPC", devc->analog_frame_size) != SR_OK)
 223                 return SR_ERR;
 224         if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK)
 225                 return SR_ERR;
 226         /*
 227          * If we get an "Execution error" the scope went from "Single" to
 228          * "Stop" without actually triggering. There is no waveform
 229          * displayed and trying to download one will fail - the scope thinks
 230          * it has 1400 samples (like display memory) and the driver thinks
 231          * it has a different number of samples.
 232          *
 233          * In that case just try to capture something again. Might still
 234          * fail in interesting ways.
 235          *
 236          * Ain't firmware fun?
 237          */
 238         if (tmp & 0x10) {
 239                 sr_warn("Single shot acquisition failed, retrying...");
 240                 /* Sleep a bit, otherwise the single shot will often fail */
 241                 g_usleep(500000);
 242                 sr_scpi_send(sdi->conn, ":SING");
 243                 rigol_ds_set_wait_event(devc, WAIT_STOP);
 244                 return SR_ERR;
 245         }
 246
 247         return SR_OK;
 248 }
 249
 250 /* Wait for enough data becoming available in scope output buffer */
 251 static int rigol_ds_block_wait(const struct sr_dev_inst *sdi)
 252 {
 253         char *buf;
 254         struct dev_context *devc;
 255         time_t start;
 256         int len;
 257
 258         if (!(devc = sdi->priv))
 259                 return SR_ERR;
 260
 261         start = time(NULL);
 262
 263         do {
 264                 if (time(NULL) - start >= 3) {
 265                         sr_dbg("Timeout waiting for data block");
 266                         return SR_ERR_TIMEOUT;
 267                 }
 268
 269                 /*
 270                  * The scope copies data really slowly from sample
 271                  * memory to its output buffer, so try not to bother
 272                  * it too much with SCPI requests but don't wait too
 273                  * long for short sample frame sizes.
 274                  */
 275                 g_usleep(devc->analog_frame_size < 15000 ? 100000 : 1000000);
 276
 277                 /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */
 278                 if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK)
 279                         return SR_ERR;
 280
 281                 if (parse_int(buf + 5, &len) != SR_OK)
 282                         return SR_ERR;
 283         } while (buf[0] == 'R' && len < 1000000);
 284
 285         rigol_ds_set_wait_event(devc, WAIT_NONE);
 286
 287         return SR_OK;
 288 }
 289
 290 /* Start capturing a new frameset */
 291 SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
 292 {
 293         struct dev_context *devc;
 294
 295         if (!(devc = sdi->priv))
 296                 return SR_ERR;
 297
 298         sr_dbg("Starting data capture for frameset %lu of %lu",
 299                devc->num_frames + 1, devc->limit_frames);
 300
 301         if (sr_scpi_send(sdi->conn, ":WAV:FORM BYTE") != SR_OK)
 302                 return SR_ERR;
 303         if (devc->data_source == DATA_SOURCE_LIVE) {
 304                 if (sr_scpi_send(sdi->conn, ":WAV:MODE NORM") != SR_OK)
 305                         return SR_ERR;
 306                 rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
 307         } else {
 308                 if (sr_scpi_send(sdi->conn, ":WAV:MODE RAW") != SR_OK)
 309                         return SR_ERR;
 310                 if (sr_scpi_send(sdi->conn, ":SING", devc->analog_frame_size) != SR_OK)
 311                         return SR_ERR;
 312                 rigol_ds_set_wait_event(devc, WAIT_STOP);
 313         }
 314
 315         return SR_OK;
 316 }
 317
 318 /* Start reading data from the current channel */
 319 SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi)
 320 {
 321         struct dev_context *devc;
 322         struct sr_probe *probe;
 323
 324         if (!(devc = sdi->priv))
 325                 return SR_ERR;
 326
 327         probe = devc->channel_entry->data;
 328
 329         sr_dbg("Starting reading data from channel %d", probe->index + 1);
 330
 331         if (devc->model->series < RIGOL_DS1000Z) {
 332                 if (probe->type == SR_PROBE_LOGIC) {
 333                         if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK)
 334                                 return SR_ERR;
 335                 } else {
 336                         if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d",
 337                                         probe->index + 1) != SR_OK)
 338                                 return SR_ERR;
 339                 }
 340         } else {
 341                 if (sr_scpi_send(sdi->conn, ":WAV:SOUR CHAN%d",
 342                                   probe->index + 1) != SR_OK)
 343                         return SR_ERR;
 344                 if (devc->data_source != DATA_SOURCE_LIVE) {
 345                         if (sr_scpi_send(sdi->conn, ":WAV:RES") != SR_OK)
 346                                 return SR_ERR;
 347                         if (sr_scpi_send(sdi->conn, ":WAV:BEG") != SR_OK)
 348                                 return SR_ERR;
 349                         rigol_ds_set_wait_event(devc, WAIT_BLOCK);
 350                 } else
 351                         rigol_ds_set_wait_event(devc, WAIT_NONE);
 352         }
 353
 354         devc->num_frame_samples = 0;
 355         devc->num_block_bytes = 0;
 356
 357         return SR_OK;
 358 }
 359
 360 /* Read the header of a data block */
 361 static int rigol_ds_read_header(struct sr_scpi_dev_inst *scpi)
 362 {
 363         char start[3], length[10];
 364         int len, tmp;
 365
 366         /* Read the hashsign and length digit. */
 367         tmp = sr_scpi_read_data(scpi, start, 2);
 368         start[2] = '\0';
 369         if (tmp != 2) {
 370                 sr_err("Failed to read first two bytes of data block header.");
 371                 return -1;
 372         }
 373         if (start[0] != '#' || !isdigit(start[1]) || start[1] == '0') {
 374                 sr_err("Received invalid data block header start '%s'.", start);
 375                 return -1;
 376         }
 377         len = atoi(start + 1);
 378
 379         /* Read the data length. */
 380         tmp = sr_scpi_read_data(scpi, length, len);
 381         length[len] = '\0';
 382         if (tmp != len) {
 383                 sr_err("Failed to read %d bytes of data block length.", len);
 384                 return -1;
 385         }
 386         if (parse_int(length, &len) != SR_OK) {
 387                 sr_err("Received invalid data block length '%s'.", length);
 388                 return -1;
 389         }
 390
 391         sr_dbg("Received data block header: %s%s -> block length %d", start, length, len);
 392
 393         return len;
 394 }
 395
 396 SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data)
 397 {
 398         struct sr_dev_inst *sdi;
 399         struct sr_scpi_dev_inst *scpi;
 400         struct dev_context *devc;
 401         struct sr_datafeed_packet packet;
 402         struct sr_datafeed_analog analog;
 403         struct sr_datafeed_logic logic;
 404         double vdiv, offset;
 405         int len, i, vref;
 406         struct sr_probe *probe;
 407
 408         (void)fd;
 409
 410         if (!(sdi = cb_data))
 411                 return TRUE;
 412
 413         if (!(devc = sdi->priv))
 414                 return TRUE;
 415
 416         scpi = sdi->conn;
 417
 418         if (revents == G_IO_IN || revents == 0) {
 419                 if (devc->model->series >= RIGOL_DS1000Z) {
 420                         switch(devc->wait_event) {
 421                         case WAIT_NONE:
 422                                 break;
 423                         case WAIT_TRIGGER:
 424                                 if (rigol_ds_trigger_wait(sdi) != SR_OK)
 425                                         return TRUE;
 426                                 if (rigol_ds_channel_start(sdi) != SR_OK)
 427                                         return TRUE;
 428                                 break;
 429                         case WAIT_BLOCK:
 430                                 if (rigol_ds_block_wait(sdi) != SR_OK)
 431                                         return TRUE;
 432                                 break;
 433                         case WAIT_STOP:
 434                                 if (rigol_ds_stop_wait(sdi) != SR_OK)
 435                                         return TRUE;
 436                                 if (rigol_ds_check_stop(sdi) != SR_OK)
 437                                         return TRUE;
 438                                 if (rigol_ds_channel_start(sdi) != SR_OK)
 439                                         return TRUE;
 440                                 return TRUE;
 441                         default:
 442                                 sr_err("BUG: Unknown event target encountered");
 443                         }
 444                 }
 445
 446                 probe = devc->channel_entry->data;
 447
 448                 if (devc->num_block_bytes == 0 &&
 449                     devc->model->series >= RIGOL_DS1000Z) {
 450                                 if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK)
 451                                         return TRUE;
 452                 }
 453
 454                 if (devc->num_block_bytes == 0) {
 455                         if (sr_scpi_read_begin(scpi) != SR_OK)
 456                                 return TRUE;
 457                         if (devc->model->protocol == PROTOCOL_IEEE488_2) {
 458                                 sr_dbg("New block header expected");
 459                                 len = rigol_ds_read_header(scpi);
 460                                 if (len == -1)
 461                                         return TRUE;
 462                                 /* At slow timebases in live capture the DS2072
 463                                  * sometimes returns "short" data blocks, with
 464                                  * apparently no way to get the rest of the data.
 465                                  * Discard these, the complete data block will
 466                                  * appear eventually.
 467                                  */
 468                                 if (devc->data_source == DATA_SOURCE_LIVE
 469                                                 && (unsigned)len < devc->num_frame_samples) {
 470                                         sr_dbg("Discarding short data block");
 471                                         sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1);
 472                                         return TRUE;
 473                                 }
 474                                 devc->num_block_bytes = len;
 475                         } else {
 476                                 devc->num_block_bytes = probe->type == SR_PROBE_ANALOG ?
 477                                         devc->analog_frame_size : devc->digital_frame_size;
 478                         }
 479                         devc->num_block_read = 0;
 480                 }
 481
 482                 len = devc->num_block_bytes - devc->num_block_read;
 483                 len = sr_scpi_read_data(scpi, (char *)devc->buffer,
 484                                 len < ACQ_BUFFER_SIZE ? len : ACQ_BUFFER_SIZE);
 485
 486                 sr_dbg("Received %d bytes.", len);
 487                 if (len == -1)
 488                         return TRUE;
 489
 490                 devc->num_block_read += len;
 491
 492                 if (devc->num_frame_samples == 0) {
 493                         /* Start of a new frame. */
 494                         packet.type = SR_DF_FRAME_BEGIN;
 495                         sr_session_send(sdi, &packet);
 496                 }
 497
 498                 if (probe->type == SR_PROBE_ANALOG) {
 499                         vref = devc->vert_reference[probe->index];
 500                         vdiv = devc->vdiv[probe->index] / 25.6;
 501                         offset = devc->vert_offset[probe->index];
 502                         if (devc->model->series >= RIGOL_DS1000Z)
 503                                 for (i = 0; i < len; i++)
 504                                         devc->data[i] = ((int)devc->buffer[i] - vref) * vdiv - offset;
 505                         else
 506                                 for (i = 0; i < len; i++)
 507                                         devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset;
 508                         analog.probes = g_slist_append(NULL, probe);
 509                         analog.num_samples = len;
 510                         analog.data = devc->data;
 511                         analog.mq = SR_MQ_VOLTAGE;
 512                         analog.unit = SR_UNIT_VOLT;
 513                         analog.mqflags = 0;
 514                         packet.type = SR_DF_ANALOG;
 515                         packet.payload = &analog;
 516                         sr_session_send(cb_data, &packet);
 517                         g_slist_free(analog.probes);
 518                 } else {
 519                         logic.length = len;
 520                         logic.unitsize = 2;
 521                         logic.data = devc->buffer;
 522                         packet.type = SR_DF_LOGIC;
 523                         packet.payload = &logic;
 524                         sr_session_send(cb_data, &packet);
 525                 }
 526
 527                 if (devc->num_block_read == devc->num_block_bytes) {
 528                         sr_dbg("Block has been completed");
 529                         if (devc->model->series >= RIGOL_DS1000Z) {
 530                                 /* Discard the terminating linefeed */
 531                                 sr_scpi_read_data(scpi, (char *)devc->buffer, 1);
 532                         }
 533                         if (devc->model->protocol == PROTOCOL_IEEE488_2) {
 534                                 /* Prepare for possible next block */
 535                                 devc->num_block_bytes = 0;
 536                                 if (devc->data_source != DATA_SOURCE_LIVE)
 537                                         rigol_ds_set_wait_event(devc, WAIT_BLOCK);
 538                         }
 539                         if (!sr_scpi_read_complete(scpi)) {
 540                                 sr_err("Read should have been completed");
 541                                 sdi->driver->dev_acquisition_stop(sdi, cb_data);
 542                                 return TRUE;
 543                         }
 544                         devc->num_block_read = 0;
 545                 } else {
 546                         sr_dbg("%d of %d block bytes read", devc->num_block_read, devc->num_block_bytes);
 547                 }
 548
 549                 devc->num_frame_samples += len;
 550
 551                 if (devc->num_frame_samples < (probe->type == SR_PROBE_ANALOG ?
 552                                         devc->analog_frame_size : devc->digital_frame_size))
 553                         /* Don't have the whole frame yet. */
 554                         return TRUE;
 555
 556                 /* End of the frame. */
 557                 sr_dbg("Frame completed, %d samples", devc->num_frame_samples);
 558                 packet.type = SR_DF_FRAME_END;
 559                 sr_session_send(sdi, &packet);
 560                 if (devc->model->series >= RIGOL_DS1000Z) {
 561                         /* Signal end of data download to scope */
 562                         if (devc->data_source != DATA_SOURCE_LIVE)
 563                                 /*
 564                                  * This causes a query error, without it switching
 565                                  * to the next channel causes an error. Fun with
 566                                  * firmware...
 567                                  */
 568                                 sr_scpi_send(sdi->conn, ":WAV:END");
 569                 }
 570
 571                 if (probe->type == SR_PROBE_ANALOG
 572                                 && devc->channel_entry->next != NULL) {
 573                         /* We got the frame for this analog channel, but
 574                          * there's another analog channel. */
 575                         devc->channel_entry = devc->channel_entry->next;
 576                         rigol_ds_channel_start(sdi);
 577                 } else {
 578                         /* Done with all analog channels in this frame. */
 579                         if (devc->enabled_digital_probes
 580                                         && devc->channel_entry != devc->enabled_digital_probes) {
 581                                 /* Now we need to get the digital data. */
 582                                 devc->channel_entry = devc->enabled_digital_probes;
 583                                 rigol_ds_channel_start(sdi);
 584                         } else if (++devc->num_frames == devc->limit_frames) {
 585                                 sdi->driver->dev_acquisition_stop(sdi, cb_data);
 586                         } else {
 587                                 /* Get the next frame, starting with the first analog channel. */
 588                                 if (devc->enabled_analog_probes)
 589                                         devc->channel_entry = devc->enabled_analog_probes;
 590                                 else
 591                                         devc->channel_entry = devc->enabled_digital_probes;
 592
 593                                 if (devc->model->series < RIGOL_DS1000Z)
 594                                         rigol_ds_channel_start(sdi);
 595                                 else
 596                                         rigol_ds_capture_start(sdi);
 597                         }
 598                 }
 599         }
 600
 601         return TRUE;
 602 }
 603
 604 SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi)
 605 {
 606         struct dev_context *devc;
 607         char *t_s, *cmd;
 608         unsigned int i;
 609         int res;
 610
 611         devc = sdi->priv;
 612
 613         /* Analog channel state. */
 614         for (i = 0; i < devc->model->analog_channels; i++) {
 615                 cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1);
 616                 res = sr_scpi_get_string(sdi->conn, cmd, &t_s);
 617                 g_free(cmd);
 618                 if (res != SR_OK)
 619                         return SR_ERR;
 620                 devc->analog_channels[i] = !strcmp(t_s, "ON") || !strcmp(t_s, "1");
 621         }
 622         sr_dbg("Current analog channel state:");
 623         for (i = 0; i < devc->model->analog_channels; i++)
 624                 sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off");
 625
 626         /* Digital channel state. */
 627         if (devc->model->has_digital) {
 628                 if (sr_scpi_get_string(sdi->conn, ":LA:DISP?", &t_s) != SR_OK)
 629                         return SR_ERR;
 630                 devc->la_enabled = !strcmp(t_s, "ON") ? TRUE : FALSE;
 631                 sr_dbg("Logic analyzer %s, current digital channel state:",
 632                                 devc->la_enabled ? "enabled" : "disabled");
 633                 for (i = 0; i < 16; i++) {
 634                         cmd = g_strdup_printf(":DIG%d:TURN?", i);
 635                         res = sr_scpi_get_string(sdi->conn, cmd, &t_s);
 636                         g_free(cmd);
 637                         if (res != SR_OK)
 638                                 return SR_ERR;
 639                         devc->digital_channels[i] = !strcmp(t_s, "ON") ? TRUE : FALSE;
 640                         g_free(t_s);
 641                         sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off");
 642                 }
 643         }
 644
 645         /* Timebase. */
 646         if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK)
 647                 return SR_ERR;
 648         sr_dbg("Current timebase %g", devc->timebase);
 649
 650         /* Vertical gain. */
 651         for (i = 0; i < devc->model->analog_channels; i++) {
 652                 cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1);
 653                 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]);
 654                 g_free(cmd);
 655                 if (res != SR_OK)
 656                         return SR_ERR;
 657         }
 658         sr_dbg("Current vertical gain:");
 659         for (i = 0; i < devc->model->analog_channels; i++)
 660                 sr_dbg("CH%d %g", i + 1, devc->vdiv[i]);
 661
 662         sr_dbg("Current vertical reference:");
 663         if (devc->model->series >= RIGOL_DS1000Z) {
 664                 /* Vertical reference - not certain if this is the place to read it. */
 665                 for (i = 0; i < devc->model->analog_channels; i++) {
 666                         if (sr_scpi_send(sdi->conn, ":WAV:SOUR CHAN%d", i + 1) != SR_OK)
 667                                 return SR_ERR;
 668                         if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?", &devc->vert_reference[i]) != SR_OK)
 669                                 return SR_ERR;
 670                         sr_dbg("CH%d %d", i + 1, devc->vert_reference[i]);
 671                 }
 672         }
 673
 674         /* Vertical offset. */
 675         for (i = 0; i < devc->model->analog_channels; i++) {
 676                 cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1);
 677                 res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]);
 678                 g_free(cmd);
 679                 if (res != SR_OK)
 680                         return SR_ERR;
 681         }
 682         sr_dbg("Current vertical offset:");
 683         for (i = 0; i < devc->model->analog_channels; i++)
 684                 sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]);
 685
 686         /* Coupling. */
 687         for (i = 0; i < devc->model->analog_channels; i++) {
 688                 cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1);
 689                 res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]);
 690                 g_free(cmd);
 691                 if (res != SR_OK)
 692                         return SR_ERR;
 693         }
 694         sr_dbg("Current coupling:");
 695         for (i = 0; i < devc->model->analog_channels; i++)
 696                 sr_dbg("CH%d %s", i + 1, devc->coupling[i]);
 697
 698         /* Trigger source. */
 699         if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK)
 700                 return SR_ERR;
 701         sr_dbg("Current trigger source %s", devc->trigger_source);
 702
 703         /* Horizontal trigger position. */
 704         if (sr_scpi_get_float(sdi->conn, ":TIM:OFFS?", &devc->horiz_triggerpos) != SR_OK)
 705                 return SR_ERR;
 706         sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos);
 707
 708         /* Trigger slope. */
 709         if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK)
 710                 return SR_ERR;
 711         sr_dbg("Current trigger slope %s", devc->trigger_slope);
 712
 713         return SR_OK;
 714 }