2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define USB_MODEL_VERSION ""
40 #define TRIGGER_TYPE "rf10"
41 #define NUM_CHANNELS 16
43 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44 static struct sr_dev_driver *di = &asix_sigma_driver_info;
45 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
47 static const uint64_t samplerates[] = {
61 * Channel numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
65 static const char *channel_names[NUM_CHANNELS + 1] = {
66 "1", "2", "3", "4", "5", "6", "7", "8",
67 "9", "10", "11", "12", "13", "14", "15", "16",
71 static const int32_t hwcaps[] = {
72 SR_CONF_LOGIC_ANALYZER,
75 SR_CONF_CAPTURE_RATIO,
79 /* Force the FPGA to reboot. */
80 static uint8_t suicide[] = {
81 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
84 /* Prepare to upload firmware (FPGA specific). */
85 static uint8_t init_array[] = {
86 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
89 /* Initialize the logic analyzer mode. */
90 static uint8_t logic_mode_start[] = {
91 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
92 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
95 static const char *firmware_files[] = {
96 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
97 "asix-sigma-100.fw", /* 100 MHz */
98 "asix-sigma-200.fw", /* 200 MHz */
99 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
100 "asix-sigma-phasor.fw", /* Frequency counter */
103 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
107 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
109 sr_err("ftdi_read_data failed: %s",
110 ftdi_get_error_string(&devc->ftdic));
116 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
120 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
122 sr_err("ftdi_write_data failed: %s",
123 ftdi_get_error_string(&devc->ftdic));
124 } else if ((size_t) ret != size) {
125 sr_err("ftdi_write_data did not complete write.");
131 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
132 struct dev_context *devc)
135 uint8_t buf[len + 2];
138 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
139 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
141 for (i = 0; i < len; ++i) {
142 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
143 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
146 return sigma_write(buf, idx, devc);
149 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
151 return sigma_write_register(reg, &value, 1, devc);
154 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
155 struct dev_context *devc)
159 buf[0] = REG_ADDR_LOW | (reg & 0xf);
160 buf[1] = REG_ADDR_HIGH | (reg >> 4);
161 buf[2] = REG_READ_ADDR;
163 sigma_write(buf, sizeof(buf), devc);
165 return sigma_read(data, len, devc);
168 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
172 if (1 != sigma_read_register(reg, &value, 1, devc)) {
173 sr_err("sigma_get_register: 1 byte expected");
180 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
181 struct dev_context *devc)
184 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 REG_READ_ADDR | NEXT_REG,
195 sigma_write(buf, sizeof(buf), devc);
197 sigma_read(result, sizeof(result), devc);
199 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
200 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
202 /* Not really sure why this must be done, but according to spec. */
203 if ((--*stoppos & 0x1ff) == 0x1ff)
206 if ((*--triggerpos & 0x1ff) == 0x1ff)
212 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
213 uint8_t *data, struct dev_context *devc)
219 /* Send the startchunk. Index start with 1. */
220 buf[0] = startchunk >> 8;
221 buf[1] = startchunk & 0xff;
222 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
225 buf[idx++] = REG_DRAM_BLOCK;
226 buf[idx++] = REG_DRAM_WAIT_ACK;
228 for (i = 0; i < numchunks; ++i) {
229 /* Alternate bit to copy from DRAM to cache. */
230 if (i != (numchunks - 1))
231 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
233 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
235 if (i != (numchunks - 1))
236 buf[idx++] = REG_DRAM_WAIT_ACK;
239 sigma_write(buf, idx, devc);
241 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
244 /* Upload trigger look-up tables to Sigma. */
245 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
251 /* Transpose the table and send to Sigma. */
252 for (i = 0; i < 16; ++i) {
257 if (lut->m2d[0] & bit)
259 if (lut->m2d[1] & bit)
261 if (lut->m2d[2] & bit)
263 if (lut->m2d[3] & bit)
273 if (lut->m0d[0] & bit)
275 if (lut->m0d[1] & bit)
277 if (lut->m0d[2] & bit)
279 if (lut->m0d[3] & bit)
282 if (lut->m1d[0] & bit)
284 if (lut->m1d[1] & bit)
286 if (lut->m1d[2] & bit)
288 if (lut->m1d[3] & bit)
291 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
293 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
296 /* Send the parameters */
297 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
298 sizeof(lut->params), devc);
303 /* Generate the bitbang stream for programming the FPGA. */
304 static int bin2bitbang(const char *filename,
305 unsigned char **buf, size_t *buf_size)
308 unsigned long file_size;
309 unsigned long offset = 0;
312 unsigned long fwsize = 0;
313 const int buffer_size = 65536;
316 uint32_t imm = 0x3f6df2ab;
318 f = g_fopen(filename, "rb");
320 sr_err("g_fopen(\"%s\", \"rb\")", filename);
324 if (-1 == fseek(f, 0, SEEK_END)) {
325 sr_err("fseek on %s failed", filename);
330 file_size = ftell(f);
332 fseek(f, 0, SEEK_SET);
334 if (!(firmware = g_try_malloc(buffer_size))) {
335 sr_err("%s: firmware malloc failed", __func__);
337 return SR_ERR_MALLOC;
340 while ((c = getc(f)) != EOF) {
341 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
342 firmware[fwsize++] = c ^ imm;
346 if(fwsize != file_size) {
347 sr_err("%s: Error reading firmware", filename);
353 *buf_size = fwsize * 2 * 8;
355 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
357 sr_err("%s: buf/p malloc failed", __func__);
359 return SR_ERR_MALLOC;
362 for (i = 0; i < fwsize; ++i) {
363 for (bit = 7; bit >= 0; --bit) {
364 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
365 p[offset++] = v | 0x01;
372 if (offset != *buf_size) {
374 sr_err("Error reading firmware %s "
375 "offset=%ld, file_size=%ld, buf_size=%zd.",
376 filename, offset, file_size, *buf_size);
384 static void clear_helper(void *priv)
386 struct dev_context *devc;
390 ftdi_deinit(&devc->ftdic);
393 static int dev_clear(void)
395 return std_dev_clear(di, clear_helper);
398 static int init(struct sr_context *sr_ctx)
400 return std_init(sr_ctx, di, LOG_PREFIX);
403 static GSList *scan(GSList *options)
405 struct sr_dev_inst *sdi;
406 struct sr_channel *ch;
407 struct drv_context *drvc;
408 struct dev_context *devc;
410 struct ftdi_device_list *devlist;
421 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
422 sr_err("%s: devc malloc failed", __func__);
426 ftdi_init(&devc->ftdic);
428 /* Look for SIGMAs. */
430 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
431 USB_VENDOR, USB_PRODUCT)) <= 0) {
433 sr_err("ftdi_usb_find_all(): %d", ret);
437 /* Make sure it's a version 1 or 2 SIGMA. */
438 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
439 serial_txt, sizeof(serial_txt));
440 sscanf(serial_txt, "%x", &serial);
442 if (serial < 0xa6010000 || serial > 0xa602ffff) {
443 sr_err("Only SIGMA and SIGMA2 are supported "
444 "in this version of libsigrok.");
448 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
450 devc->cur_samplerate = 0;
452 devc->limit_msec = 0;
453 devc->cur_firmware = -1;
454 devc->num_channels = 0;
455 devc->samples_per_event = 0;
456 devc->capture_ratio = 50;
457 devc->use_triggers = 0;
459 /* Register SIGMA device. */
460 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
461 USB_MODEL_NAME, USB_MODEL_VERSION))) {
462 sr_err("%s: sdi was NULL", __func__);
467 for (i = 0; channel_names[i]; i++) {
468 if (!(ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
471 sdi->channels = g_slist_append(sdi->channels, ch);
474 devices = g_slist_append(devices, sdi);
475 drvc->instances = g_slist_append(drvc->instances, sdi);
478 /* We will open the device again when we need it. */
479 ftdi_list_free(&devlist);
484 ftdi_deinit(&devc->ftdic);
489 static GSList *dev_list(void)
491 return ((struct drv_context *)(di->priv))->instances;
494 static int upload_firmware(int firmware_idx, struct dev_context *devc)
500 unsigned char result[32];
501 char firmware_path[128];
503 /* Make sure it's an ASIX SIGMA. */
504 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
505 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
506 sr_err("ftdi_usb_open failed: %s",
507 ftdi_get_error_string(&devc->ftdic));
511 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
512 sr_err("ftdi_set_bitmode failed: %s",
513 ftdi_get_error_string(&devc->ftdic));
517 /* Four times the speed of sigmalogan - Works well. */
518 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
519 sr_err("ftdi_set_baudrate failed: %s",
520 ftdi_get_error_string(&devc->ftdic));
524 /* Force the FPGA to reboot. */
525 sigma_write(suicide, sizeof(suicide), devc);
526 sigma_write(suicide, sizeof(suicide), devc);
527 sigma_write(suicide, sizeof(suicide), devc);
528 sigma_write(suicide, sizeof(suicide), devc);
530 /* Prepare to upload firmware (FPGA specific). */
531 sigma_write(init_array, sizeof(init_array), devc);
533 ftdi_usb_purge_buffers(&devc->ftdic);
535 /* Wait until the FPGA asserts INIT_B. */
537 ret = sigma_read(result, 1, devc);
538 if (result[0] & 0x20)
542 /* Prepare firmware. */
543 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
544 firmware_files[firmware_idx]);
546 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
547 sr_err("An error occured while reading the firmware: %s",
552 /* Upload firmare. */
553 sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
554 sigma_write(buf, buf_size, devc);
558 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
559 sr_err("ftdi_set_bitmode failed: %s",
560 ftdi_get_error_string(&devc->ftdic));
564 ftdi_usb_purge_buffers(&devc->ftdic);
566 /* Discard garbage. */
567 while (1 == sigma_read(&pins, 1, devc))
570 /* Initialize the logic analyzer mode. */
571 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
573 /* Expect a 3 byte reply. */
574 ret = sigma_read(result, 3, devc);
576 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
577 sr_err("Configuration failed. Invalid reply received.");
581 devc->cur_firmware = firmware_idx;
583 sr_info("Firmware uploaded.");
588 static int dev_open(struct sr_dev_inst *sdi)
590 struct dev_context *devc;
595 /* Make sure it's an ASIX SIGMA. */
596 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
597 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
599 sr_err("ftdi_usb_open failed: %s",
600 ftdi_get_error_string(&devc->ftdic));
605 sdi->status = SR_ST_ACTIVE;
610 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
612 struct dev_context *devc;
619 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
620 if (samplerates[i] == samplerate)
623 if (samplerates[i] == 0)
624 return SR_ERR_SAMPLERATE;
626 if (samplerate <= SR_MHZ(50)) {
627 ret = upload_firmware(0, devc);
628 devc->num_channels = 16;
630 if (samplerate == SR_MHZ(100)) {
631 ret = upload_firmware(1, devc);
632 devc->num_channels = 8;
634 else if (samplerate == SR_MHZ(200)) {
635 ret = upload_firmware(2, devc);
636 devc->num_channels = 4;
639 devc->cur_samplerate = samplerate;
640 devc->period_ps = 1000000000000ULL / samplerate;
641 devc->samples_per_event = 16 / devc->num_channels;
642 devc->state.state = SIGMA_IDLE;
648 * In 100 and 200 MHz mode, only a single pin rising/falling can be
649 * set as trigger. In other modes, two rising/falling triggers can be set,
650 * in addition to value/mask trigger for any number of channels.
652 * The Sigma supports complex triggers using boolean expressions, but this
653 * has not been implemented yet.
655 static int configure_channels(const struct sr_dev_inst *sdi)
657 struct dev_context *devc = sdi->priv;
658 const struct sr_channel *ch;
663 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
665 for (l = sdi->channels; l; l = l->next) {
666 ch = (struct sr_channel *)l->data;
667 channelbit = 1 << (ch->index);
669 if (!ch->enabled || !ch->trigger)
672 if (devc->cur_samplerate >= SR_MHZ(100)) {
673 /* Fast trigger support. */
675 sr_err("Only a single pin trigger in 100 and "
676 "200MHz mode is supported.");
679 if (ch->trigger[0] == 'f')
680 devc->trigger.fallingmask |= channelbit;
681 else if (ch->trigger[0] == 'r')
682 devc->trigger.risingmask |= channelbit;
684 sr_err("Only rising/falling trigger in 100 "
685 "and 200MHz mode is supported.");
691 /* Simple trigger support (event). */
692 if (ch->trigger[0] == '1') {
693 devc->trigger.simplevalue |= channelbit;
694 devc->trigger.simplemask |= channelbit;
696 else if (ch->trigger[0] == '0') {
697 devc->trigger.simplevalue &= ~channelbit;
698 devc->trigger.simplemask |= channelbit;
700 else if (ch->trigger[0] == 'f') {
701 devc->trigger.fallingmask |= channelbit;
704 else if (ch->trigger[0] == 'r') {
705 devc->trigger.risingmask |= channelbit;
710 * Actually, Sigma supports 2 rising/falling triggers,
711 * but they are ORed and the current trigger syntax
712 * does not permit ORed triggers.
714 if (trigger_set > 1) {
715 sr_err("Only 1 rising/falling trigger "
722 devc->use_triggers = 1;
728 static int dev_close(struct sr_dev_inst *sdi)
730 struct dev_context *devc;
735 if (sdi->status == SR_ST_ACTIVE)
736 ftdi_usb_close(&devc->ftdic);
738 sdi->status = SR_ST_INACTIVE;
743 static int cleanup(void)
748 static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
749 const struct sr_channel_group *cg)
751 struct dev_context *devc;
756 case SR_CONF_SAMPLERATE:
759 *data = g_variant_new_uint64(devc->cur_samplerate);
770 static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
771 const struct sr_channel_group *cg)
773 struct dev_context *devc;
778 if (sdi->status != SR_ST_ACTIVE)
779 return SR_ERR_DEV_CLOSED;
783 if (id == SR_CONF_SAMPLERATE) {
784 ret = set_samplerate(sdi, g_variant_get_uint64(data));
785 } else if (id == SR_CONF_LIMIT_MSEC) {
786 devc->limit_msec = g_variant_get_uint64(data);
787 if (devc->limit_msec > 0)
791 } else if (id == SR_CONF_CAPTURE_RATIO) {
792 devc->capture_ratio = g_variant_get_uint64(data);
793 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
804 static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
805 const struct sr_channel_group *cg)
814 case SR_CONF_DEVICE_OPTIONS:
815 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
816 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
818 case SR_CONF_SAMPLERATE:
819 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
820 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
821 ARRAY_SIZE(samplerates), sizeof(uint64_t));
822 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
823 *data = g_variant_builder_end(&gvb);
825 case SR_CONF_TRIGGER_TYPE:
826 *data = g_variant_new_string(TRIGGER_TYPE);
835 /* Software trigger to determine exact trigger position. */
836 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
837 struct sigma_trigger *t)
841 for (i = 0; i < 8; ++i) {
843 last_sample = samples[i-1];
845 /* Simple triggers. */
846 if ((samples[i] & t->simplemask) != t->simplevalue)
850 if ((last_sample & t->risingmask) != 0 || (samples[i] &
851 t->risingmask) != t->risingmask)
855 if ((last_sample & t->fallingmask) != t->fallingmask ||
856 (samples[i] & t->fallingmask) != 0)
862 /* If we did not match, return original trigger pos. */
867 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
868 * Each event is 20ns apart, and can contain multiple samples.
870 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
871 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
872 * For 50 MHz and below, events contain one sample for each channel,
873 * spread 20 ns apart.
875 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
876 uint16_t *lastsample, int triggerpos,
877 uint16_t limit_chunk, void *cb_data)
879 struct sr_dev_inst *sdi = cb_data;
880 struct dev_context *devc = sdi->priv;
882 uint16_t samples[65536 * devc->samples_per_event];
883 struct sr_datafeed_packet packet;
884 struct sr_datafeed_logic logic;
885 int i, j, k, l, numpad, tosend;
886 size_t n = 0, sent = 0;
887 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
892 /* Check if trigger is in this chunk. */
893 if (triggerpos != -1) {
894 if (devc->cur_samplerate <= SR_MHZ(50))
895 triggerpos -= EVENTS_PER_CLUSTER - 1;
900 /* Find in which cluster the trigger occured. */
901 triggerts = triggerpos / 7;
905 for (i = 0; i < 64; ++i) {
906 ts = *(uint16_t *) &buf[i * 16];
907 tsdiff = ts - *lastts;
910 /* Decode partial chunk. */
911 if (limit_chunk && ts > limit_chunk)
914 /* Pad last sample up to current point. */
915 numpad = tsdiff * devc->samples_per_event - clustersize;
917 for (j = 0; j < numpad; ++j)
918 samples[j] = *lastsample;
923 /* Send samples between previous and this timestamp to sigrok. */
926 tosend = MIN(2048, n - sent);
928 packet.type = SR_DF_LOGIC;
929 packet.payload = &logic;
930 logic.length = tosend * sizeof(uint16_t);
932 logic.data = samples + sent;
933 sr_session_send(devc->cb_data, &packet);
939 event = (uint16_t *) &buf[i * 16 + 2];
942 /* For each event in cluster. */
943 for (j = 0; j < 7; ++j) {
945 /* For each sample in event. */
946 for (k = 0; k < devc->samples_per_event; ++k) {
949 /* For each channel. */
950 for (l = 0; l < devc->num_channels; ++l)
951 cur_sample |= (!!(event[j] & (1 << (l *
952 devc->samples_per_event + k)))) << l;
954 samples[n++] = cur_sample;
958 /* Send data up to trigger point (if triggered). */
960 if (i == triggerts) {
962 * Trigger is not always accurate to sample because of
963 * pipeline delay. However, it always triggers before
964 * the actual event. We therefore look at the next
965 * samples to pinpoint the exact position of the trigger.
967 tosend = get_trigger_offset(samples, *lastsample,
971 packet.type = SR_DF_LOGIC;
972 packet.payload = &logic;
973 logic.length = tosend * sizeof(uint16_t);
975 logic.data = samples;
976 sr_session_send(devc->cb_data, &packet);
981 /* Only send trigger if explicitly enabled. */
982 if (devc->use_triggers) {
983 packet.type = SR_DF_TRIGGER;
984 sr_session_send(devc->cb_data, &packet);
988 /* Send rest of the chunk to sigrok. */
992 packet.type = SR_DF_LOGIC;
993 packet.payload = &logic;
994 logic.length = tosend * sizeof(uint16_t);
996 logic.data = samples + sent;
997 sr_session_send(devc->cb_data, &packet);
1000 *lastsample = samples[n - 1];
1006 static int receive_data(int fd, int revents, void *cb_data)
1008 struct sr_dev_inst *sdi = cb_data;
1009 struct dev_context *devc = sdi->priv;
1010 struct sr_datafeed_packet packet;
1011 const int chunks_per_read = 32;
1012 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1013 int bufsz, numchunks, i, newchunks;
1014 uint64_t running_msec;
1020 /* Get the current position. */
1021 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1023 numchunks = (devc->state.stoppos + 511) / 512;
1025 if (devc->state.state == SIGMA_IDLE)
1028 if (devc->state.state == SIGMA_CAPTURE) {
1029 /* Check if the timer has expired, or memory is full. */
1030 gettimeofday(&tv, 0);
1031 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1032 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1034 if (running_msec < devc->limit_msec && numchunks < 32767)
1035 return TRUE; /* While capturing... */
1037 dev_acquisition_stop(sdi, sdi);
1041 if (devc->state.state == SIGMA_DOWNLOAD) {
1042 if (devc->state.chunks_downloaded >= numchunks) {
1043 /* End of samples. */
1044 packet.type = SR_DF_END;
1045 sr_session_send(devc->cb_data, &packet);
1047 devc->state.state = SIGMA_IDLE;
1052 newchunks = MIN(chunks_per_read,
1053 numchunks - devc->state.chunks_downloaded);
1055 sr_info("Downloading sample data: %.0f %%.",
1056 100.0 * devc->state.chunks_downloaded / numchunks);
1058 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1059 newchunks, buf, devc);
1060 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1063 /* Find first ts. */
1064 if (devc->state.chunks_downloaded == 0) {
1065 devc->state.lastts = RL16(buf) - 1;
1066 devc->state.lastsample = 0;
1069 /* Decode chunks and send them to sigrok. */
1070 for (i = 0; i < newchunks; ++i) {
1071 int limit_chunk = 0;
1073 /* The last chunk may potentially be only in part. */
1074 if (devc->state.chunks_downloaded == numchunks - 1) {
1075 /* Find the last valid timestamp */
1076 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1079 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1080 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1081 &devc->state.lastts,
1082 &devc->state.lastsample,
1083 devc->state.triggerpos & 0x1ff,
1086 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1087 &devc->state.lastts,
1088 &devc->state.lastsample,
1089 -1, limit_chunk, sdi);
1091 ++devc->state.chunks_downloaded;
1098 /* Build a LUT entry used by the trigger functions. */
1099 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1103 /* For each quad channel. */
1104 for (i = 0; i < 4; ++i) {
1107 /* For each bit in LUT. */
1108 for (j = 0; j < 16; ++j)
1110 /* For each channel in quad. */
1111 for (k = 0; k < 4; ++k) {
1112 bit = 1 << (i * 4 + k);
1114 /* Set bit in entry */
1116 ((!(value & bit)) !=
1118 entry[i] &= ~(1 << j);
1123 /* Add a logical function to LUT mask. */
1124 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1125 int index, int neg, uint16_t *mask)
1128 int x[2][2], tmp, a, b, aset, bset, rset;
1130 memset(x, 0, 4 * sizeof(int));
1132 /* Trigger detect condition. */
1162 case OP_NOTRISEFALL:
1168 /* Transpose if neg is set. */
1170 for (i = 0; i < 2; ++i) {
1171 for (j = 0; j < 2; ++j) {
1173 x[i][j] = x[1-i][1-j];
1179 /* Update mask with function. */
1180 for (i = 0; i < 16; ++i) {
1181 a = (i >> (2 * index + 0)) & 1;
1182 b = (i >> (2 * index + 1)) & 1;
1184 aset = (*mask >> i) & 1;
1187 if (func == FUNC_AND || func == FUNC_NAND)
1189 else if (func == FUNC_OR || func == FUNC_NOR)
1191 else if (func == FUNC_XOR || func == FUNC_NXOR)
1194 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1205 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1206 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1207 * set at any time, but a full mask and value can be set (0/1).
1209 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1212 uint16_t masks[2] = { 0, 0 };
1214 memset(lut, 0, sizeof(struct triggerlut));
1216 /* Contant for simple triggers. */
1219 /* Value/mask trigger support. */
1220 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1223 /* Rise/fall trigger support. */
1224 for (i = 0, j = 0; i < 16; ++i) {
1225 if (devc->trigger.risingmask & (1 << i) ||
1226 devc->trigger.fallingmask & (1 << i))
1227 masks[j++] = 1 << i;
1230 build_lut_entry(masks[0], masks[0], lut->m0d);
1231 build_lut_entry(masks[1], masks[1], lut->m1d);
1233 /* Add glue logic */
1234 if (masks[0] || masks[1]) {
1235 /* Transition trigger. */
1236 if (masks[0] & devc->trigger.risingmask)
1237 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1238 if (masks[0] & devc->trigger.fallingmask)
1239 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1240 if (masks[1] & devc->trigger.risingmask)
1241 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1242 if (masks[1] & devc->trigger.fallingmask)
1243 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1245 /* Only value/mask trigger. */
1249 /* Triggertype: event. */
1250 lut->params.selres = 3;
1255 static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1257 struct dev_context *devc;
1258 struct clockselect_50 clockselect;
1259 int frac, triggerpin, ret;
1260 uint8_t triggerselect = 0;
1261 struct triggerinout triggerinout_conf;
1262 struct triggerlut lut;
1264 if (sdi->status != SR_ST_ACTIVE)
1265 return SR_ERR_DEV_CLOSED;
1269 if (configure_channels(sdi) != SR_OK) {
1270 sr_err("Failed to configure channels.");
1274 /* If the samplerate has not been set, default to 200 kHz. */
1275 if (devc->cur_firmware == -1) {
1276 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1280 /* Enter trigger programming mode. */
1281 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1283 /* 100 and 200 MHz mode. */
1284 if (devc->cur_samplerate >= SR_MHZ(100)) {
1285 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1287 /* Find which pin to trigger on from mask. */
1288 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1289 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1293 /* Set trigger pin and light LED on trigger. */
1294 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1296 /* Default rising edge. */
1297 if (devc->trigger.fallingmask)
1298 triggerselect |= 1 << 3;
1300 /* All other modes. */
1301 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1302 build_basic_trigger(&lut, devc);
1304 sigma_write_trigger_lut(&lut, devc);
1306 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1309 /* Setup trigger in and out pins to default values. */
1310 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1311 triggerinout_conf.trgout_bytrigger = 1;
1312 triggerinout_conf.trgout_enable = 1;
1314 sigma_write_register(WRITE_TRIGGER_OPTION,
1315 (uint8_t *) &triggerinout_conf,
1316 sizeof(struct triggerinout), devc);
1318 /* Go back to normal mode. */
1319 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1321 /* Set clock select register. */
1322 if (devc->cur_samplerate == SR_MHZ(200))
1323 /* Enable 4 channels. */
1324 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1325 else if (devc->cur_samplerate == SR_MHZ(100))
1326 /* Enable 8 channels. */
1327 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1330 * 50 MHz mode (or fraction thereof). Any fraction down to
1331 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1333 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1335 clockselect.async = 0;
1336 clockselect.fraction = frac;
1337 clockselect.disabled_channels = 0;
1339 sigma_write_register(WRITE_CLOCK_SELECT,
1340 (uint8_t *) &clockselect,
1341 sizeof(clockselect), devc);
1344 /* Setup maximum post trigger time. */
1345 sigma_set_register(WRITE_POST_TRIGGER,
1346 (devc->capture_ratio * 255) / 100, devc);
1348 /* Start acqusition. */
1349 gettimeofday(&devc->start_tv, 0);
1350 sigma_set_register(WRITE_MODE, 0x0d, devc);
1352 devc->cb_data = cb_data;
1354 /* Send header packet to the session bus. */
1355 std_session_send_df_header(cb_data, LOG_PREFIX);
1357 /* Add capture source. */
1358 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1360 devc->state.state = SIGMA_CAPTURE;
1365 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1367 struct dev_context *devc;
1372 sr_source_remove(0);
1374 if (!(devc = sdi->priv)) {
1375 sr_err("%s: sdi->priv was NULL", __func__);
1379 /* Stop acquisition. */
1380 sigma_set_register(WRITE_MODE, 0x11, devc);
1382 /* Set SDRAM Read Enable. */
1383 sigma_set_register(WRITE_MODE, 0x02, devc);
1385 /* Get the current position. */
1386 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1388 /* Check if trigger has fired. */
1389 modestatus = sigma_get_register(READ_MODE, devc);
1390 if (modestatus & 0x20)
1391 devc->state.triggerchunk = devc->state.triggerpos / 512;
1393 devc->state.triggerchunk = -1;
1395 devc->state.chunks_downloaded = 0;
1397 devc->state.state = SIGMA_DOWNLOAD;
1402 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1403 .name = "asix-sigma",
1404 .longname = "ASIX SIGMA/SIGMA2",
1409 .dev_list = dev_list,
1410 .dev_clear = dev_clear,
1411 .config_get = config_get,
1412 .config_set = config_set,
1413 .config_list = config_list,
1414 .dev_open = dev_open,
1415 .dev_close = dev_close,
1416 .dev_acquisition_start = dev_acquisition_start,
1417 .dev_acquisition_stop = dev_acquisition_stop,