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drivers: Factor out std_gvar_samplerates{,_steps}().
[libsigrok.git] / src / hardware / openbench-logic-sniffer / api.c
CommitLineData
0aba65da 1/*
50985c20 2 * This file is part of the libsigrok project.
0aba65da 3 *
13d8e03c 4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
0aba65da
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
6ec6c43b 20#include <config.h>
515ab088 21#include "protocol.h"
0aba65da
UH
22
23#define SERIALCOMM "115200/8n1"
24
a0e0bb41 25static const uint32_t scanopts[] = {
1953564a
BV
26 SR_CONF_CONN,
27 SR_CONF_SERIALCOMM,
aeabd308
UH
28};
29
55fb76b3
UH
30static const uint32_t drvopts[] = {
31 SR_CONF_LOGIC_ANALYZER,
32};
33
f254bc4b 34static const uint32_t devopts[] = {
5827f61b
BV
35 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
36 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
37 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
38 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
39 SR_CONF_EXTERNAL_CLOCK | SR_CONF_SET,
40 SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
41 SR_CONF_SWAP | SR_CONF_SET,
42 SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
0aba65da
UH
43};
44
91fd0f72
BV
45static const int32_t trigger_matches[] = {
46 SR_TRIGGER_ZERO,
47 SR_TRIGGER_ONE,
48};
49
6d16fdfb
BV
50#define STR_PATTERN_NONE "None"
51#define STR_PATTERN_EXTERNAL "External"
52#define STR_PATTERN_INTERNAL "Internal"
967760a8
MR
53
54/* Supported methods of test pattern outputs */
55enum {
56 /**
57 * Capture pins 31:16 (unbuffered wing) output a test pattern
58 * that can captured on pins 0:15.
59 */
60 PATTERN_EXTERNAL,
61
62 /** Route test pattern internally to capture buffer. */
63 PATTERN_INTERNAL,
64};
65
7c07a178 66static const char *patterns[] = {
6d16fdfb 67 STR_PATTERN_NONE,
7c07a178
UH
68 STR_PATTERN_EXTERNAL,
69 STR_PATTERN_INTERNAL,
70};
71
ba7dd8bb 72/* Channels are numbered 0-31 (on the PCB silkscreen). */
53cda65a 73SR_PRIV const char *ols_channel_names[] = {
78693401
UH
74 "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
75 "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
76 "24", "25", "26", "27", "28", "29", "30", "31",
0aba65da
UH
77};
78
d3b38ad3 79/* Default supported samplerates, can be overridden by device metadata. */
e46aa4f6
BV
80static const uint64_t samplerates[] = {
81 SR_HZ(10),
82 SR_MHZ(200),
83 SR_HZ(1),
0aba65da
UH
84};
85
1a46cc62
UH
86#define RESPONSE_DELAY_US (10 * 1000)
87
4f840ce9 88static GSList *scan(struct sr_dev_driver *di, GSList *options)
0aba65da 89{
1987b8d6 90 struct sr_config *src;
0aba65da 91 struct sr_dev_inst *sdi;
0aba65da 92 struct sr_serial_dev_inst *serial;
43376f33 93 GSList *l;
07ffa5b3
UH
94 int ret;
95 unsigned int i;
0aba65da
UH
96 const char *conn, *serialcomm;
97 char buf[8];
98
0aba65da
UH
99 conn = serialcomm = NULL;
100 for (l = options; l; l = l->next) {
1987b8d6
BV
101 src = l->data;
102 switch (src->key) {
1953564a 103 case SR_CONF_CONN:
e46aa4f6 104 conn = g_variant_get_string(src->data, NULL);
0aba65da 105 break;
1953564a 106 case SR_CONF_SERIALCOMM:
e46aa4f6 107 serialcomm = g_variant_get_string(src->data, NULL);
0aba65da
UH
108 break;
109 }
110 }
111 if (!conn)
112 return NULL;
113
98fec29e 114 if (!serialcomm)
0aba65da
UH
115 serialcomm = SERIALCOMM;
116
91219afc 117 serial = sr_serial_dev_inst_new(conn, serialcomm);
0aba65da
UH
118
119 /* The discovery procedure is like this: first send the Reset
120 * command (0x00) 5 times, since the device could be anywhere
121 * in a 5-byte command. Then send the ID command (0x02).
122 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
123 * have a match.
124 */
125 sr_info("Probing %s.", conn);
4ded59ee 126 if (serial_open(serial, SERIAL_RDWR) != SR_OK)
0aba65da
UH
127 return NULL;
128
244995a2 129 if (ols_send_reset(serial) != SR_OK) {
0aba65da
UH
130 serial_close(serial);
131 sr_err("Could not use port %s. Quitting.", conn);
132 return NULL;
133 }
134 send_shortcommand(serial, CMD_ID);
135
1a46cc62 136 g_usleep(RESPONSE_DELAY_US);
0aba65da 137
ed936ccc
UH
138 if (sp_input_waiting(serial->data) == 0) {
139 sr_dbg("Didn't get any reply.");
0aba65da 140 return NULL;
ed936ccc
UH
141 }
142
143 ret = serial_read_blocking(serial, buf, 4, serial_timeout(serial, 4));
144 if (ret != 4) {
145 sr_err("Invalid reply (expected 4 bytes, got %d).", ret);
0aba65da 146 return NULL;
ed936ccc
UH
147 }
148
149 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) {
150 sr_err("Invalid reply (expected '1SLO' or '1ALS', got "
151 "'%c%c%c%c').", buf[0], buf[1], buf[2], buf[3]);
0aba65da 152 return NULL;
ed936ccc 153 }
0aba65da
UH
154
155 /* Definitely using the OLS protocol, check if it supports
156 * the metadata command.
157 */
158 send_shortcommand(serial, CMD_METADATA);
ed936ccc 159
1a46cc62 160 g_usleep(RESPONSE_DELAY_US);
ed936ccc
UH
161
162 if (sp_input_waiting(serial->data) != 0) {
0aba65da
UH
163 /* Got metadata. */
164 sdi = get_metadata(serial);
0aba65da
UH
165 } else {
166 /* Not an OLS -- some other board that uses the sump protocol. */
72cd99b8 167 sr_info("Device does not support metadata.");
aac29cc1 168 sdi = g_malloc0(sizeof(struct sr_dev_inst));
0af636be
UH
169 sdi->status = SR_ST_INACTIVE;
170 sdi->vendor = g_strdup("Sump");
171 sdi->model = g_strdup("Logic Analyzer");
172 sdi->version = g_strdup("v1.0");
07ffa5b3 173 for (i = 0; i < ARRAY_SIZE(ols_channel_names); i++)
5e23fcab 174 sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
c368e6f3 175 ols_channel_names[i]);
e57057ae 176 sdi->priv = ols_dev_new();
0aba65da 177 }
bf256783
BV
178 /* Configure samplerate and divider. */
179 if (ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
180 sr_dbg("Failed to set default samplerate (%"PRIu64").",
181 DEFAULT_SAMPLERATE);
459a0f26
BV
182 sdi->inst_type = SR_INST_SERIAL;
183 sdi->conn = serial;
bf256783 184
0aba65da
UH
185 serial_close(serial);
186
43376f33 187 return std_scan_complete(di, g_slist_append(NULL, sdi));
0aba65da
UH
188}
189
584560f1 190static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
53b4680f 191 const struct sr_channel_group *cg)
0aba65da
UH
192{
193 struct dev_context *devc;
194
53b4680f 195 (void)cg;
8f996b89 196
0c05591a
BV
197 if (!sdi)
198 return SR_ERR_ARG;
199
200 devc = sdi->priv;
584560f1 201 switch (key) {
123e1313 202 case SR_CONF_SAMPLERATE:
0c05591a
BV
203 *data = g_variant_new_uint64(devc->cur_samplerate);
204 break;
205 case SR_CONF_CAPTURE_RATIO:
206 *data = g_variant_new_uint64(devc->capture_ratio);
207 break;
208 case SR_CONF_LIMIT_SAMPLES:
209 *data = g_variant_new_uint64(devc->limit_samples);
210 break;
967760a8
MR
211 case SR_CONF_PATTERN_MODE:
212 if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
213 *data = g_variant_new_string(STR_PATTERN_EXTERNAL);
214 else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
215 *data = g_variant_new_string(STR_PATTERN_INTERNAL);
6d16fdfb
BV
216 else
217 *data = g_variant_new_string(STR_PATTERN_NONE);
967760a8 218 break;
0c05591a
BV
219 case SR_CONF_RLE:
220 *data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
7730e4f0 221 break;
0aba65da 222 default:
bd6fbf62 223 return SR_ERR_NA;
0aba65da
UH
224 }
225
226 return SR_OK;
227}
228
584560f1 229static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
53b4680f 230 const struct sr_channel_group *cg)
0aba65da
UH
231{
232 struct dev_context *devc;
6d16fdfb 233 uint16_t flag;
e46aa4f6 234 uint64_t tmp_u64;
6d16fdfb 235 int ret;
967760a8 236 const char *stropt;
0aba65da 237
53b4680f 238 (void)cg;
8f996b89 239
0aba65da
UH
240 devc = sdi->priv;
241
584560f1 242 switch (key) {
1953564a 243 case SR_CONF_SAMPLERATE:
e46aa4f6
BV
244 tmp_u64 = g_variant_get_uint64(data);
245 if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1])
246 return SR_ERR_SAMPLERATE;
247 ret = ols_set_samplerate(sdi, g_variant_get_uint64(data));
0aba65da 248 break;
1953564a 249 case SR_CONF_LIMIT_SAMPLES:
e46aa4f6
BV
250 tmp_u64 = g_variant_get_uint64(data);
251 if (tmp_u64 < MIN_NUM_SAMPLES)
0aba65da 252 return SR_ERR;
e46aa4f6 253 devc->limit_samples = tmp_u64;
0aba65da
UH
254 ret = SR_OK;
255 break;
1953564a 256 case SR_CONF_CAPTURE_RATIO:
e46aa4f6 257 devc->capture_ratio = g_variant_get_uint64(data);
a5c38703 258 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
0aba65da 259 ret = SR_ERR;
a5c38703 260 else
0aba65da
UH
261 ret = SR_OK;
262 break;
eb1b610b
MR
263 case SR_CONF_EXTERNAL_CLOCK:
264 if (g_variant_get_boolean(data)) {
265 sr_info("Enabling external clock.");
266 devc->flag_reg |= FLAG_CLOCK_EXTERNAL;
267 } else {
268 sr_info("Disabled external clock.");
269 devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
270 }
271 ret = SR_OK;
272 break;
967760a8
MR
273 case SR_CONF_PATTERN_MODE:
274 stropt = g_variant_get_string(data, NULL);
275 ret = SR_OK;
6d16fdfb
BV
276 flag = 0xffff;
277 if (!strcmp(stropt, STR_PATTERN_NONE)) {
278 sr_info("Disabling test modes.");
279 flag = 0x0000;
280 }else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
967760a8 281 sr_info("Enabling internal test mode.");
6d16fdfb 282 flag = FLAG_INTERNAL_TEST_MODE;
967760a8
MR
283 } else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
284 sr_info("Enabling external test mode.");
6d16fdfb 285 flag = FLAG_EXTERNAL_TEST_MODE;
967760a8
MR
286 } else {
287 ret = SR_ERR;
288 }
6d16fdfb
BV
289 if (flag != 0xffff) {
290 devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE);
291 devc->flag_reg |= flag;
292 }
967760a8 293 break;
7b0a57fd
MR
294 case SR_CONF_SWAP:
295 if (g_variant_get_boolean(data)) {
296 sr_info("Enabling channel swapping.");
3f239f08 297 devc->flag_reg |= FLAG_SWAP_CHANNELS;
7b0a57fd
MR
298 } else {
299 sr_info("Disabling channel swapping.");
3f239f08 300 devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
7b0a57fd
MR
301 }
302 ret = SR_OK;
303 break;
304
1953564a 305 case SR_CONF_RLE:
e46aa4f6 306 if (g_variant_get_boolean(data)) {
0aba65da
UH
307 sr_info("Enabling RLE.");
308 devc->flag_reg |= FLAG_RLE;
aeea0572
BV
309 } else {
310 sr_info("Disabling RLE.");
311 devc->flag_reg &= ~FLAG_RLE;
0aba65da
UH
312 }
313 ret = SR_OK;
314 break;
315 default:
bd6fbf62 316 ret = SR_ERR_NA;
0aba65da
UH
317 }
318
319 return ret;
320}
321
584560f1 322static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
53b4680f 323 const struct sr_channel_group *cg)
a1c743fc 324{
f0de2dd0 325 struct dev_context *devc;
463160cb 326 GVariant *grange[2];
91fd0f72 327 int num_ols_changrp, i;
a1c743fc 328
a1c743fc 329 switch (key) {
0d485e30 330 case SR_CONF_SCAN_OPTIONS:
9a6517d1 331 case SR_CONF_DEVICE_OPTIONS:
e66d1892 332 return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
a1c743fc 333 case SR_CONF_SAMPLERATE:
463160cb 334 *data = std_gvar_samplerates_steps(samplerates, ARRAY_SIZE(samplerates));
a1c743fc 335 break;
91fd0f72
BV
336 case SR_CONF_TRIGGER_MATCH:
337 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
338 trigger_matches, ARRAY_SIZE(trigger_matches),
339 sizeof(int32_t));
c50277a6 340 break;
7c07a178
UH
341 case SR_CONF_PATTERN_MODE:
342 *data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
343 break;
f0de2dd0
BV
344 case SR_CONF_LIMIT_SAMPLES:
345 if (!sdi)
346 return SR_ERR_ARG;
347 devc = sdi->priv;
348 if (devc->flag_reg & FLAG_RLE)
349 return SR_ERR_NA;
350 if (devc->max_samples == 0)
351 /* Device didn't specify sample memory size in metadata. */
352 return SR_ERR_NA;
353 /*
ba7dd8bb 354 * Channel groups are turned off if no channels in that group are
f0de2dd0
BV
355 * enabled, making more room for samples for the enabled group.
356 */
91fd0f72
BV
357 ols_channel_mask(sdi);
358 num_ols_changrp = 0;
f0de2dd0 359 for (i = 0; i < 4; i++) {
ba7dd8bb 360 if (devc->channel_mask & (0xff << (i * 8)))
91fd0f72 361 num_ols_changrp++;
1e1dac0c 362 }
f0de2dd0 363 grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
91fd0f72
BV
364 if (num_ols_changrp)
365 grange[1] = g_variant_new_uint64(devc->max_samples / num_ols_changrp);
366 else
367 grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
f0de2dd0
BV
368 *data = g_variant_new_tuple(grange, 2);
369 break;
a1c743fc 370 default:
bd6fbf62 371 return SR_ERR_NA;
a1c743fc
BV
372 }
373
374 return SR_OK;
375}
376
016e72f3
BV
377static int set_trigger(const struct sr_dev_inst *sdi, int stage)
378{
379 struct dev_context *devc;
380 struct sr_serial_dev_inst *serial;
381 uint8_t cmd, arg[4];
382
383 devc = sdi->priv;
384 serial = sdi->conn;
385
386 cmd = CMD_SET_TRIGGER_MASK + stage * 4;
387 arg[0] = devc->trigger_mask[stage] & 0xff;
388 arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
389 arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
390 arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
391 if (send_longcommand(serial, cmd, arg) != SR_OK)
392 return SR_ERR;
393
394 cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
395 arg[0] = devc->trigger_value[stage] & 0xff;
396 arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
397 arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
398 arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
399 if (send_longcommand(serial, cmd, arg) != SR_OK)
400 return SR_ERR;
401
402 cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
403 arg[0] = arg[1] = arg[3] = 0x00;
404 arg[2] = stage;
405 if (stage == devc->num_stages)
406 /* Last stage, fire when this one matches. */
407 arg[3] |= TRIGGER_START;
408 if (send_longcommand(serial, cmd, arg) != SR_OK)
409 return SR_ERR;
410
411 return SR_OK;
412}
413
695dc859 414static int dev_acquisition_start(const struct sr_dev_inst *sdi)
0aba65da 415{
0aba65da 416 struct dev_context *devc;
459a0f26 417 struct sr_serial_dev_inst *serial;
32f09bfd 418 uint16_t samplecount, readcount, delaycount;
91fd0f72
BV
419 uint8_t ols_changrp_mask, arg[4];
420 int num_ols_changrp;
016e72f3 421 int ret, i;
0aba65da
UH
422
423 devc = sdi->priv;
459a0f26 424 serial = sdi->conn;
0aba65da 425
91fd0f72 426 ols_channel_mask(sdi);
0aba65da 427
91fd0f72
BV
428 num_ols_changrp = 0;
429 ols_changrp_mask = 0;
0aba65da 430 for (i = 0; i < 4; i++) {
ba7dd8bb 431 if (devc->channel_mask & (0xff << (i * 8))) {
91fd0f72
BV
432 ols_changrp_mask |= (1 << i);
433 num_ols_changrp++;
0aba65da
UH
434 }
435 }
436
437 /*
438 * Limit readcount to prevent reading past the end of the hardware
439 * buffer.
440 */
91fd0f72 441 samplecount = MIN(devc->max_samples / num_ols_changrp, devc->limit_samples);
32f09bfd 442 readcount = samplecount / 4;
016e72f3
BV
443
444 /* Rather read too many samples than too few. */
445 if (samplecount % 4 != 0)
32f09bfd 446 readcount++;
0aba65da 447
016e72f3 448 /* Basic triggers. */
91fd0f72
BV
449 if (ols_convert_trigger(sdi) != SR_OK) {
450 sr_err("Failed to configure channels.");
451 return SR_ERR;
452 }
453 if (devc->num_stages > 0) {
b853eb76
GGM
454 /*
455 * According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf
456 * reset command must be send prior each arm command
457 */
458 sr_dbg("Send reset command before trigger configure");
459 if (ols_send_reset(serial) != SR_OK)
460 return SR_ERR;
461
0aba65da
UH
462 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
463 devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
016e72f3 464 for (i = 0; i <= devc->num_stages; i++) {
91fd0f72 465 sr_dbg("Setting OLS stage %d trigger.", i);
016e72f3
BV
466 if ((ret = set_trigger(sdi, i)) != SR_OK)
467 return ret;
468 }
0aba65da 469 } else {
016e72f3
BV
470 /* No triggers configured, force trigger on first stage. */
471 sr_dbg("Forcing trigger at stage 0.");
472 if ((ret = set_trigger(sdi, 0)) != SR_OK)
473 return ret;
0aba65da
UH
474 delaycount = readcount;
475 }
476
6d16fdfb 477 /* Samplerate. */
016e72f3 478 sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
6d16fdfb 479 devc->cur_samplerate, devc->cur_samplerate_divider);
016e72f3
BV
480 arg[0] = devc->cur_samplerate_divider & 0xff;
481 arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
482 arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
483 arg[3] = 0x00;
484 if (send_longcommand(serial, CMD_SET_DIVIDER, arg) != SR_OK)
0aba65da
UH
485 return SR_ERR;
486
487 /* Send sample limit and pre/post-trigger capture ratio. */
016e72f3 488 sr_dbg("Setting sample limit %d, trigger point at %d",
6d16fdfb 489 (readcount - 1) * 4, (delaycount - 1) * 4);
016e72f3
BV
490 arg[0] = ((readcount - 1) & 0xff);
491 arg[1] = ((readcount - 1) & 0xff00) >> 8;
492 arg[2] = ((delaycount - 1) & 0xff);
493 arg[3] = ((delaycount - 1) & 0xff00) >> 8;
494 if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
0aba65da
UH
495 return SR_ERR;
496
6d16fdfb 497 /* Flag register. */
625763e2
BV
498 sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
499 devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
6d16fdfb 500 devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
625763e2
BV
501 devc->flag_reg & FLAG_RLE ? "on" : "off",
502 devc->flag_reg & FLAG_FILTER ? "on": "off",
503 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
91fd0f72
BV
504 /*
505 * Enable/disable OLS channel groups in the flag register according
506 * to the channel mask. 1 means "disable channel".
507 */
508 devc->flag_reg |= ~(ols_changrp_mask << 2) & 0x3c;
016e72f3
BV
509 arg[0] = devc->flag_reg & 0xff;
510 arg[1] = devc->flag_reg >> 8;
511 arg[2] = arg[3] = 0x00;
512 if (send_longcommand(serial, CMD_SET_FLAGS, arg) != SR_OK)
0aba65da
UH
513 return SR_ERR;
514
515 /* Start acquisition on the device. */
459a0f26 516 if (send_shortcommand(serial, CMD_RUN) != SR_OK)
0aba65da
UH
517 return SR_ERR;
518
bf256783 519 /* Reset all operational states. */
6d16fdfb
BV
520 devc->rle_count = devc->num_transfers = 0;
521 devc->num_samples = devc->num_bytes = 0;
625763e2 522 devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
abb39e6b 523 memset(devc->sample, 0, 4);
bf256783 524
bee2b016 525 std_session_send_df_header(sdi);
4afdfd46 526
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527 /* If the device stops sending for longer than it takes to send a byte,
528 * that means it's finished. But wait at least 100 ms to be safe.
529 */
530 serial_source_add(sdi->session, serial, G_IO_IN, 100,
695dc859 531 ols_receive_data, (struct sr_dev_inst *)sdi);
0aba65da 532
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533 return SR_OK;
534}
535
695dc859 536static int dev_acquisition_stop(struct sr_dev_inst *sdi)
0aba65da 537{
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538 abort_acquisition(sdi);
539
540 return SR_OK;
541}
542
15a5bfe4 543static struct sr_dev_driver ols_driver_info = {
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544 .name = "ols",
545 .longname = "Openbench Logic Sniffer",
546 .api_version = 1,
c2fdcc25 547 .init = std_init,
700d6b64 548 .cleanup = std_cleanup,
03f4de8c 549 .scan = scan,
c01bf34c 550 .dev_list = std_dev_list,
f778bf02 551 .dev_clear = std_dev_clear,
035a1078
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552 .config_get = config_get,
553 .config_set = config_set,
a1c743fc 554 .config_list = config_list,
854434de 555 .dev_open = std_serial_dev_open,
bf2c987f 556 .dev_close = std_serial_dev_close,
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557 .dev_acquisition_start = dev_acquisition_start,
558 .dev_acquisition_stop = dev_acquisition_stop,
41812aca 559 .context = NULL,
0aba65da 560};
dd5c48a6 561SR_REGISTER_DEV_DRIVER(ols_driver_info);