[libsigrok.git] / src / hardware / hung-chang-dso-2100 / protocol.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2015 Daniel Glöckner <daniel-gl@gmx.net>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include <ieee1284.h>
#include "protocol.h"

/* The firmware can be in the following states:
 *  0x00	Temporary state during initialization
 *  		Automatically transitions to state 0x01
 *  0x01	Idle, this state updates calibration caps
 *		Send 0x02 to go to state 0x21
 *		Send 0x03 to go to state 0x03
 *		Send 0x04 to go to state 0x14
 *  0x21	Trigger is armed, caps are _not_ updated
 *  		Send 0x99 to check if trigger event occured
 *  			if triggered, goes to state 0x03
 *  			else stays in state 0x21
 *  		Send 0xFE to generate artificial trigger event
 *			returns to state 0x21
 *			but next 0x99 will succeed
 *		Send 0xFF to go to state 0x03 (abort capture)
 *  0x03	Extracts two 500 sample subsets from the 5000
 *  		sample capture buffer for readout
 *  		When reading samples, the FPGA starts at the
 *  		first of the 1000 samples and automatically
 *  		advances to the next.
 *  		Send 0x04 to go to state 0x0F
 *  0x14	Scroll acquisition mode, update calib caps
 *  		When reading samples, the FPGA provides the
 *  		current value of the ADCs
 *  		Send 0xFF to go to state 0x0F
 *  0x0F	Send channel number (1 or 2) to go to next state
 *  		There are actually two 0x0F states in series
 *  		which both expect the channel number.
 *  		If the values don't match, they are discarded.
 *  		The next state 0x05 is entered anyway
 *  0x05	Same as state 0x0F but expects sample rate index.
 *  		The next state is 0x08
 *  0x08	Same as state 0x0F but expects step size + 1 for
 *  		the second 500 sample subset
 *  		The next state is 0x09
 *  0x09	Same as state 0x0F but expects step size + 1 for
 *  		the first 500 sample subset
 *  		The next state is 0x06
 *  0x06	Same as state 0x0F but expects vdiv and coupling
 *  		configuration for the first channel and trigger
 *  		source selection.
 *  		(U46 in the schematics)
 *  		The next state is 0x07
 *  0x07	Same as state 0x0F but expects vdiv and coupling
 *  		configuration for the first channel and trigger
 *  		type (edge, TV hsync, TV vsync).
 *  		(U47 in the schematics)
 *  		The next state is 0x0A
 *  0x0A	Same as state 0x0F but expects a parameter X + 1
 *  		that determines the offset of the second 500 sample
 *  		subset
 *  		Offset = 5 * X * step size for first subset
 *  		The next state is 0x0B
 *  0x0B	Same as state 0x0F but expects the type of edge to
 *  		trigger on (rising or falling)
 *  		The next state is 0x0C
 *  0x0C	Same as state 0x0F but expects the calibration
 *  		value for the first channel's  position
 *  		(POS1 in the schematics)
 *  		The next state is 0x0D
 *  0x0D	Same as state 0x0F but expects the calibration
 *  		value for the second channel's  position
 *  		(POS2 in the schematics)
 *  		The next state is 0x0E
 *  0x0E	Same as state 0x0F but expects the trigger level
 *  		(TRIGLEVEL in the schematics)
 *  		Keep in mind that trigger sources are AC coupled
 *  		The next state is 0x10
 *  0x10	Same as state 0x0F but expects the calibration
 *  		value for the first channel's offset
 *  		(OFFSET1 in the schematics)
 *  		The next state is 0x11
 *  0x11	Same as state 0x0F but expects the calibration
 *  		value for the first channel's gain
 *  		(GAIN1 in the schematics)
 *  		The next state is 0x12
 *  0x12	Same as state 0x0F but expects the calibration
 *  		value for the second channel's offset
 *  		(OFFSET2 in the schematics)
 *  		The next state is 0x13
 *  0x13	Same as state 0x0F but expects the calibration
 *  		value for the second channel's gain
 *  		(GAIN2 in the schematics)
 *  		The next state is 0x01
 *
 * The Mailbox appears to be half duplex.
 * If one side writes a byte into the mailbox, it
 * reads 0 until the other side has written a byte.
 * So you can't transfer 0.
 *
 * As the status signals are unconnected, the device is not
 * IEEE1284 compliant and can't make use of EPP or ECP transfers.
 * It drives the data lines when control is set to:
 *                0                => Channel A data
 *          C1284_NAUTOFD          => Channel B data
 *         C1284_NSELECTIN         => Mailbox
 * C1284_NSELECTIN | C1284_NAUTOFD => 0x55
 *
 * It takes about 200ns for the data lines to become stable after
 * the control lines have been changed. This driver assumes that
 * parallel port access is slow enough to not require additional
 * delays.
 *
 * Channel values in state 0x14 and the mailbox can change their
 * value while they are selected, the latter of course only from
 * 0 to a valid state. Beware of intermediate values.
 *
 * SRAM N layout (N = 1 or 2):
 * 0x0000-0x13ff	samples captured from ADC N
 * 0x4000-0x41f3	bytes extracted from 0x6000 with step1
 *			(both ADCs but only channel N)
 * 0x41f4-0x43e7	bytes extracted from 0x6000+5*step1*shift
 *			with step2 (both ADCs but only channel N)
 * 0x43e8-0x43ea	{0x01, 0xfe, 0x80}
 * 0x43eb-0x444e	copy of bytes from 0x4320
 * 0x6000-0x7387	interleaved SRAM 1 and SRAM 2 bytes from
 * 			0x0001 to 0x09c5 after channel N was captured
 *
 * On a trigger event the FPGA directs the ADC samples to the region
 * at 0x0000. The microcontroller then copies 5000 samples from 0x0001
 * to 0x6000. Each time state 0x03 is entered, the bytes from 0x4000
 * to 0x444e are filled and the start address for readout is reset to
 * 0x4000. Readout will wrap around back to 0x4000 after reaching 0x7fff.
 *
 * As you can see from the layout, it was probably intended to capture
 * 5000 samples for both probes before they are read out. We don't do that
 * to be able to read the full 10k samples captured by the FPGA. It would
 * be useless anyway if you don't capture repetitive signals. We're also
 * not reading the two samples at 0x0000 to save a few milliseconds.
 */

static const struct {
	uint16_t num;
	uint8_t step1;
	uint8_t shift;
	uint8_t interleave;
} readout_steps[] = {
	{ 1000, 1, 100, 0 },
	{ 500, 100, 2, 0 },
	{ 500, 100, 3, 0 },
	{ 500, 100, 4, 0 },
	{ 500, 100, 5, 0 },
	{ 500, 100, 6, 0 },
	{ 500, 100, 7, 0 },
	{ 500, 100, 8, 0 },
	{ 500, 100, 9, 0 },
	{ 499, 212, 41, 1 },
	{ 500, 157, 56, 1 },
	{ 500, 247, 36, 1 },
	{ 500, 232, 180, 1 },
	{ 500, 230, 182, 1 },
	{ 120, 212, 43, 1 }
};

SR_PRIV void hung_chang_dso_2100_reset_port(struct parport *port)
{
	ieee1284_write_control(port,
			C1284_NSTROBE | C1284_NAUTOFD | C1284_NSELECTIN);
	ieee1284_data_dir(port, 0);
}

SR_PRIV gboolean hung_chang_dso_2100_check_id(struct parport *port)
{
	gboolean ret = FALSE;

	if (ieee1284_data_dir(port, 1) != E1284_OK)
		goto fail;

	ieee1284_write_control(port, C1284_NSTROBE | C1284_NAUTOFD | C1284_NSELECTIN);
	ieee1284_write_control(port, C1284_NAUTOFD | C1284_NSELECTIN);

	if (ieee1284_read_data(port) != 0x55)
		goto fail;

	ret = TRUE;
fail:
	hung_chang_dso_2100_reset_port(port);

	return ret;
}

SR_PRIV void hung_chang_dso_2100_write_mbox(struct parport *port, uint8_t val)
{
	sr_dbg("mbox <= %X", val);
	ieee1284_write_control(port,
			C1284_NSTROBE | C1284_NINIT | C1284_NSELECTIN);
	ieee1284_data_dir(port, 0);
	ieee1284_write_data(port, val);
	ieee1284_write_control(port, C1284_NINIT | C1284_NSELECTIN);
	ieee1284_write_control(port,
			C1284_NSTROBE | C1284_NINIT | C1284_NSELECTIN);
	ieee1284_data_dir(port, 1);
	ieee1284_write_control(port,
		C1284_NSTROBE | C1284_NAUTOFD | C1284_NINIT | C1284_NSELECTIN);
}

SR_PRIV uint8_t hung_chang_dso_2100_read_mbox(struct parport *port, float timeout)
{
	GTimer *timer = NULL;
	uint8_t val;

	ieee1284_write_control(port, C1284_NSTROBE | C1284_NSELECTIN);
	ieee1284_write_control(port, C1284_NSELECTIN);

	for (;;) {
		if (ieee1284_read_data(port)) {
			/* Always read the value a second time.
			 * The first one may be unstable. */
			val = ieee1284_read_data(port);
			break;
		}
		if (!timer) {
			timer = g_timer_new();
		} else if (g_timer_elapsed(timer, NULL) > timeout) {
			val = 0;
			break;
		}
	}

	ieee1284_write_control(port, C1284_NSTROBE | C1284_NSELECTIN);
	ieee1284_write_control(port,
		C1284_NSTROBE | C1284_NAUTOFD | C1284_NINIT | C1284_NSELECTIN);

	if (timer)
		g_timer_destroy(timer);
	sr_dbg("mbox == %X", val);
	return val;
}

SR_PRIV int hung_chang_dso_2100_move_to(const struct sr_dev_inst *sdi, uint8_t target)
{
	struct dev_context *devc = sdi->priv;
	int timeout = 40;
	uint8_t c;

	while (timeout--) {
		c = hung_chang_dso_2100_read_mbox(sdi->conn, 0.1);
		if (c == target)
			return SR_OK;

		switch (c) {
		case 0x00:
			/* Can happen if someone wrote something into
			 * the mbox that was not expected by the uC.
			 * Alternating between 0xff and 4 helps in
			 * all states. */
			c = (timeout & 1) ? 0xFF : 0x04;
			break;
		case 0x01:
			switch (target) {
			case 0x21: c = 2; break;
			case 0x03: c = 3; break;
			default: c = 4;
			}
			break;
		case 0x03: c = 4; break;
		case 0x05: c = devc->rate + 1; break;
		case 0x06: c = devc->cctl[0]; break;
		case 0x07: c = devc->cctl[1]; break;
		case 0x08: c = 1 /* step 2 */ + 1 ; break;
		case 0x09: c = readout_steps[devc->step].step1 + 1; break;
		case 0x0A: c = readout_steps[devc->step].shift + 1; break;
		case 0x0B: c = devc->edge + 1; break;
		case 0x0C: c = devc->pos[0]; break;
		case 0x0D: c = devc->pos[1]; break;
		case 0x0E: c = devc->tlevel; break;
		case 0x0F:
			if (!devc->channel)
				c = 1;
			else if (readout_steps[devc->step].interleave)
				c = devc->adc2 ? 2 : 1;
			else
				c = devc->channel;
			break;
		case 0x10: c = devc->offset[0]; break;
		case 0x11: c = devc->gain[0]; break;
		case 0x12: c = devc->offset[1]; break;
		case 0x13: c = devc->gain[1]; break;
		case 0x14:
		case 0x21: c = 0xFF; break;
		default:
			return SR_ERR_DATA;
		}
		hung_chang_dso_2100_write_mbox(sdi->conn, c);
	}
	return SR_ERR_TIMEOUT;
}

static void skip_samples(struct parport *port, uint8_t ctrl, size_t num)
{
	while (num--) {
		ieee1284_write_control(port, ctrl & ~C1284_NSTROBE);
		ieee1284_write_control(port, ctrl);
	}
}

static void read_samples(struct parport *port, uint8_t ctrl, uint8_t *buf, size_t num, size_t stride)
{
	while (num--) {
		ieee1284_write_control(port, ctrl & ~C1284_NSTROBE);
		*buf = ieee1284_read_data(port);
		buf += stride;
		ieee1284_write_control(port, ctrl);
	}
}

static void push_samples(const struct sr_dev_inst *sdi, uint8_t *buf, size_t num)
{
	struct dev_context *devc = sdi->priv;
	float *data = devc->samples;
	struct sr_datafeed_analog_old analog = {
		.channels = devc->enabled_channel,
		.num_samples = num,
		.mq = SR_MQ_VOLTAGE,
		.unit = SR_UNIT_VOLT,
		.mqflags = 0,
		.data = data,
	};
	struct sr_datafeed_packet packet = {
		.type = SR_DF_ANALOG_OLD,
		.payload = &analog,
	};
	float factor = devc->factor;

	while (num--)
		data[num] = (buf[num] - 0x80) * factor;

	sr_session_send(sdi, &packet);
}

static int read_subframe(const struct sr_dev_inst *sdi, uint8_t *buf)
{
	struct dev_context *devc = sdi->priv;
	uint8_t sig[3], ctrl;
	unsigned int num;
	gboolean interleave;

	interleave = readout_steps[devc->step].interleave;
	ctrl = C1284_NSTROBE;
	if ((interleave && devc->adc2) || (!interleave && devc->channel == 2))
		ctrl |= C1284_NAUTOFD;

	ieee1284_write_control(sdi->conn, ctrl);
	num = readout_steps[devc->step].num;
	if (num < 1000)
		skip_samples(sdi->conn, ctrl, 1000 - num);
	read_samples(sdi->conn, ctrl, buf + (devc->adc2 ? 1 : 0), num,
		     interleave ? 2 : 1);
	read_samples(sdi->conn, ctrl, sig, 3, 1);
	if (sig[0] != 0x01 || sig[1] != 0xfe || sig[2] != 0x80) {
		if (--devc->retries) {
			sr_dbg("Missing signature at end of buffer, %i tries remaining",
			       devc->retries);
			return TRUE;
		} else {
			sr_err("Failed to read frame without transfer errors");
			devc->step = 0;
		}
	} else {
		if (interleave && !devc->adc2) {
			devc->adc2 = TRUE;
			devc->retries = MAX_RETRIES;
			return TRUE;
		} else {
			if (interleave)
				num *= 2;
			if (!devc->step) {
				struct sr_datafeed_packet packet = {
					.type = SR_DF_TRIGGER
				};

				push_samples(sdi, buf, 6);
				sr_session_send(sdi, &packet);
				buf += 6;
				num -= 6;
			}
			push_samples(sdi, buf, num);
			if (++devc->step > devc->last_step)
				devc->step = 0;
		}
	}

	devc->adc2 = FALSE;
	devc->retries = MAX_RETRIES;

	return devc->step > 0;
}

SR_PRIV int hung_chang_dso_2100_poll(int fd, int revents, void *cb_data)
{
	struct sr_datafeed_packet packet = { .type = SR_DF_FRAME_BEGIN };
	const struct sr_dev_inst *sdi;
	struct dev_context *devc;
	uint8_t state, buf[1000];

	(void)fd;
	(void)revents;

	if (!(sdi = cb_data))
		return TRUE;

	if (!(devc = sdi->priv))
		return TRUE;

	if (devc->state_known)
		hung_chang_dso_2100_write_mbox(sdi->conn, 0x99);

	state = hung_chang_dso_2100_read_mbox(sdi->conn, 0.00025);
	devc->state_known = (state != 0x00);

	if (!devc->state_known || state == 0x21)
		return TRUE;

	if (state != 0x03) {
		sr_err("Unexpected state 0x%X while checking for trigger", state);
		return FALSE;
	}

	sr_session_send(sdi, &packet);

	if (devc->channel) {
		while (read_subframe(sdi, buf)) {
			if (hung_chang_dso_2100_move_to(sdi, 1) != SR_OK)
				break;
			hung_chang_dso_2100_write_mbox(sdi->conn, 3);
			g_usleep(1700);
			if (hung_chang_dso_2100_read_mbox(sdi->conn, 0.02) != 0x03)
				break;
		}
	}

	packet.type = SR_DF_FRAME_END;
	sr_session_send(sdi, &packet);

	if (++devc->frame >= devc->frame_limit)
		hung_chang_dso_2100_dev_acquisition_stop(sdi);
	else
		hung_chang_dso_2100_move_to(sdi, 0x21);

	return TRUE;
}
Commit	Line	Data
05ac4a98 DG	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2015 Daniel Glöckner <daniel-gl@gmx.net>
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
6ec6c43b	20	#include <config.h>
c9404469	21	#include <ieee1284.h>
05ac4a98 DG	22	#include "protocol.h"
05ac4a98 DG	23
c9404469 DG	24	/* The firmware can be in the following states:
	25	* 0x00 Temporary state during initialization
	26	* Automatically transitions to state 0x01
	27	* 0x01 Idle, this state updates calibration caps
	28	* Send 0x02 to go to state 0x21
	29	* Send 0x03 to go to state 0x03
	30	* Send 0x04 to go to state 0x14
	31	* 0x21 Trigger is armed, caps are _not_ updated
	32	* Send 0x99 to check if trigger event occured
	33	* if triggered, goes to state 0x03
	34	* else stays in state 0x21
	35	* Send 0xFE to generate artificial trigger event
	36	* returns to state 0x21
	37	* but next 0x99 will succeed
	38	* Send 0xFF to go to state 0x03 (abort capture)
	39	* 0x03 Extracts two 500 sample subsets from the 5000
	40	* sample capture buffer for readout
	41	* When reading samples, the FPGA starts at the
	42	* first of the 1000 samples and automatically
	43	* advances to the next.
	44	* Send 0x04 to go to state 0x0F
	45	* 0x14 Scroll acquisition mode, update calib caps
	46	* When reading samples, the FPGA provides the
	47	* current value of the ADCs
	48	* Send 0xFF to go to state 0x0F
	49	* 0x0F Send channel number (1 or 2) to go to next state
	50	* There are actually two 0x0F states in series
	51	* which both expect the channel number.
	52	* If the values don't match, they are discarded.
	53	* The next state 0x05 is entered anyway
	54	* 0x05 Same as state 0x0F but expects sample rate index.
	55	* The next state is 0x08
	56	* 0x08 Same as state 0x0F but expects step size + 1 for
	57	* the second 500 sample subset
	58	* The next state is 0x09
	59	* 0x09 Same as state 0x0F but expects step size + 1 for
	60	* the first 500 sample subset
	61	* The next state is 0x06
	62	* 0x06 Same as state 0x0F but expects vdiv and coupling
	63	* configuration for the first channel and trigger
	64	* source selection.
	65	* (U46 in the schematics)
	66	* The next state is 0x07
	67	* 0x07 Same as state 0x0F but expects vdiv and coupling
	68	* configuration for the first channel and trigger
	69	* type (edge, TV hsync, TV vsync).
	70	* (U47 in the schematics)
	71	* The next state is 0x0A
	72	* 0x0A Same as state 0x0F but expects a parameter X + 1
	73	* that determines the offset of the second 500 sample
	74	* subset
	75	* Offset = 5 * X * step size for first subset
	76	* The next state is 0x0B
	77	* 0x0B Same as state 0x0F but expects the type of edge to
	78	* trigger on (rising or falling)
	79	* The next state is 0x0C
	80	* 0x0C Same as state 0x0F but expects the calibration
	81	* value for the first channel's position
	82	* (POS1 in the schematics)
	83	* The next state is 0x0D
	84	* 0x0D Same as state 0x0F but expects the calibration
	85	* value for the second channel's position
	86	* (POS2 in the schematics)
	87	* The next state is 0x0E
88	* 0x0E Same as state 0x0F but expects the trigger level
89	* (TRIGLEVEL in the schematics)
90	* Keep in mind that trigger sources are AC coupled
91	* The next state is 0x10
92	* 0x10 Same as state 0x0F but expects the calibration
93	* value for the first channel's offset
94	* (OFFSET1 in the schematics)
95	* The next state is 0x11
96	* 0x11 Same as state 0x0F but expects the calibration
97	* value for the first channel's gain
98	* (GAIN1 in the schematics)
99	* The next state is 0x12
100	* 0x12 Same as state 0x0F but expects the calibration
101	* value for the second channel's offset
102	* (OFFSET2 in the schematics)
103	* The next state is 0x13
104	* 0x13 Same as state 0x0F but expects the calibration
105	* value for the second channel's gain
106	* (GAIN2 in the schematics)
107	* The next state is 0x01
108	*
109	* The Mailbox appears to be half duplex.
110	* If one side writes a byte into the mailbox, it
111	* reads 0 until the other side has written a byte.
112	* So you can't transfer 0.
113	*
114	* As the status signals are unconnected, the device is not
115	* IEEE1284 compliant and can't make use of EPP or ECP transfers.
116	* It drives the data lines when control is set to:
117	* 0 => Channel A data
118	* C1284_NAUTOFD => Channel B data
119	* C1284_NSELECTIN => Mailbox
120	* C1284_NSELECTIN \| C1284_NAUTOFD => 0x55
121	*
122	* It takes about 200ns for the data lines to become stable after
123	* the control lines have been changed. This driver assumes that
124	* parallel port access is slow enough to not require additional
125	* delays.
126	*
127	* Channel values in state 0x14 and the mailbox can change their
128	* value while they are selected, the latter of course only from
129	* 0 to a valid state. Beware of intermediate values.
130	*
131	* SRAM N layout (N = 1 or 2):
132	* 0x0000-0x13ff samples captured from ADC N
133	* 0x4000-0x41f3 bytes extracted from 0x6000 with step1
134	* (both ADCs but only channel N)
135	* 0x41f4-0x43e7 bytes extracted from 0x6000+5step1shift
136	* with step2 (both ADCs but only channel N)
137	* 0x43e8-0x43ea {0x01, 0xfe, 0x80}
138	* 0x43eb-0x444e copy of bytes from 0x4320
139	* 0x6000-0x7387 interleaved SRAM 1 and SRAM 2 bytes from
140	* 0x0001 to 0x09c5 after channel N was captured
141	*
142	* On a trigger event the FPGA directs the ADC samples to the region
143	* at 0x0000. The microcontroller then copies 5000 samples from 0x0001
144	* to 0x6000. Each time state 0x03 is entered, the bytes from 0x4000
145	* to 0x444e are filled and the start address for readout is reset to
146	* 0x4000. Readout will wrap around back to 0x4000 after reaching 0x7fff.
147	*
148	* As you can see from the layout, it was probably intended to capture
149	* 5000 samples for both probes before they are read out. We don't do that
150	* to be able to read the full 10k samples captured by the FPGA. It would
151	* be useless anyway if you don't capture repetitive signals. We're also
152	* not reading the two samples at 0x0000 to save a few milliseconds.
153	*/
154
155	static const struct {
156	uint16_t num;
157	uint8_t step1;
158	uint8_t shift;
159	uint8_t interleave;
160	} readout_steps[] = {
161	{ 1000, 1, 100, 0 },
162	{ 500, 100, 2, 0 },
163	{ 500, 100, 3, 0 },
164	{ 500, 100, 4, 0 },
165	{ 500, 100, 5, 0 },
166	{ 500, 100, 6, 0 },
167	{ 500, 100, 7, 0 },
168	{ 500, 100, 8, 0 },
169	{ 500, 100, 9, 0 },
170	{ 499, 212, 41, 1 },
171	{ 500, 157, 56, 1 },
172	{ 500, 247, 36, 1 },
173	{ 500, 232, 180, 1 },
174	{ 500, 230, 182, 1 },
175	{ 120, 212, 43, 1 }
176	};
177
178	SR_PRIV void hung_chang_dso_2100_reset_port(struct parport *port)
05ac4a98	179	{
c9404469 DG	180	ieee1284_write_control(port,
	181	C1284_NSTROBE \| C1284_NAUTOFD \| C1284_NSELECTIN);
	182	ieee1284_data_dir(port, 0);
	183	}
	184
	185	SR_PRIV gboolean hung_chang_dso_2100_check_id(struct parport *port)
	186	{
	187	gboolean ret = FALSE;
	188
	189	if (ieee1284_data_dir(port, 1) != E1284_OK)
	190	goto fail;
	191
	192	ieee1284_write_control(port, C1284_NSTROBE \| C1284_NAUTOFD \| C1284_NSELECTIN);
	193	ieee1284_write_control(port, C1284_NAUTOFD \| C1284_NSELECTIN);
	194
	195	if (ieee1284_read_data(port) != 0x55)
	196	goto fail;
	197
	198	ret = TRUE;
	199	fail:
	200	hung_chang_dso_2100_reset_port(port);
	201
	202	return ret;
	203	}
	204
	205	SR_PRIV void hung_chang_dso_2100_write_mbox(struct parport *port, uint8_t val)
	206	{
	207	sr_dbg("mbox <= %X", val);
	208	ieee1284_write_control(port,
	209	C1284_NSTROBE \| C1284_NINIT \| C1284_NSELECTIN);
	210	ieee1284_data_dir(port, 0);
	211	ieee1284_write_data(port, val);
	212	ieee1284_write_control(port, C1284_NINIT \| C1284_NSELECTIN);
	213	ieee1284_write_control(port,
	214	C1284_NSTROBE \| C1284_NINIT \| C1284_NSELECTIN);
	215	ieee1284_data_dir(port, 1);
	216	ieee1284_write_control(port,
	217	C1284_NSTROBE \| C1284_NAUTOFD \| C1284_NINIT \| C1284_NSELECTIN);
	218	}
	219
	220	SR_PRIV uint8_t hung_chang_dso_2100_read_mbox(struct parport *port, float timeout)
	221	{
	222	GTimer *timer = NULL;
	223	uint8_t val;
	224
	225	ieee1284_write_control(port, C1284_NSTROBE \| C1284_NSELECTIN);
	226	ieee1284_write_control(port, C1284_NSELECTIN);
	227
	228	for (;;) {
	229	if (ieee1284_read_data(port)) {
	230	/* Always read the value a second time.
	231	* The first one may be unstable. */
	232	val = ieee1284_read_data(port);
	233	break;
	234	}
	235	if (!timer) {
	236	timer = g_timer_new();
	237	} else if (g_timer_elapsed(timer, NULL) > timeout) {
	238	val = 0;
	239	break;
	240	}
	241	}
	242
	243	ieee1284_write_control(port, C1284_NSTROBE \| C1284_NSELECTIN);
244	ieee1284_write_control(port,
245	C1284_NSTROBE \| C1284_NAUTOFD \| C1284_NINIT \| C1284_NSELECTIN);
246
247	if (timer)
248	g_timer_destroy(timer);
249	sr_dbg("mbox == %X", val);
250	return val;
251	}
252
253	SR_PRIV int hung_chang_dso_2100_move_to(const struct sr_dev_inst *sdi, uint8_t target)
254	{
255	struct dev_context *devc = sdi->priv;
256	int timeout = 40;
257	uint8_t c;
258
259	while (timeout--) {
260	c = hung_chang_dso_2100_read_mbox(sdi->conn, 0.1);
261	if (c == target)
262	return SR_OK;
263
264	switch (c) {
265	case 0x00:
266	/* Can happen if someone wrote something into
267	* the mbox that was not expected by the uC.
268	* Alternating between 0xff and 4 helps in
269	* all states. */
270	c = (timeout & 1) ? 0xFF : 0x04;
271	break;
272	case 0x01:
273	switch (target) {
274	case 0x21: c = 2; break;
275	case 0x03: c = 3; break;
276	default: c = 4;
277	}
278	break;
279	case 0x03: c = 4; break;
280	case 0x05: c = devc->rate + 1; break;
281	case 0x06: c = devc->cctl[0]; break;
282	case 0x07: c = devc->cctl[1]; break;
283	case 0x08: c = 1 /* step 2 */ + 1 ; break;
284	case 0x09: c = readout_steps[devc->step].step1 + 1; break;
285	case 0x0A: c = readout_steps[devc->step].shift + 1; break;
286	case 0x0B: c = devc->edge + 1; break;
287	case 0x0C: c = devc->pos[0]; break;
288	case 0x0D: c = devc->pos[1]; break;
289	case 0x0E: c = devc->tlevel; break;
290	case 0x0F:
291	if (!devc->channel)
292	c = 1;
293	else if (readout_steps[devc->step].interleave)
294	c = devc->adc2 ? 2 : 1;
295	else
296	c = devc->channel;
297	break;
298	case 0x10: c = devc->offset[0]; break;
299	case 0x11: c = devc->gain[0]; break;
300	case 0x12: c = devc->offset[1]; break;
301	case 0x13: c = devc->gain[1]; break;
302	case 0x14:
303	case 0x21: c = 0xFF; break;
304	default:
305	return SR_ERR_DATA;
306	}
307	hung_chang_dso_2100_write_mbox(sdi->conn, c);
308	}
309	return SR_ERR_TIMEOUT;
310	}
311
312	static void skip_samples(struct parport *port, uint8_t ctrl, size_t num)
313	{
314	while (num--) {
315	ieee1284_write_control(port, ctrl & ~C1284_NSTROBE);
316	ieee1284_write_control(port, ctrl);
317	}
318	}
319
320	static void read_samples(struct parport port, uint8_t ctrl, uint8_t buf, size_t num, size_t stride)
321	{
322	while (num--) {
323	ieee1284_write_control(port, ctrl & ~C1284_NSTROBE);
324	*buf = ieee1284_read_data(port);
325	buf += stride;
326	ieee1284_write_control(port, ctrl);
327	}
328	}
329
330	static void push_samples(const struct sr_dev_inst sdi, uint8_t buf, size_t num)
331	{
332	struct dev_context *devc = sdi->priv;
333	float *data = devc->samples;
5faebab2	334	struct sr_datafeed_analog_old analog = {
c9404469 DG	335	.channels = devc->enabled_channel,
	336	.num_samples = num,
	337	.mq = SR_MQ_VOLTAGE,
	338	.unit = SR_UNIT_VOLT,
	339	.mqflags = 0,
	340	.data = data,
	341	};
	342	struct sr_datafeed_packet packet = {
5faebab2	343	.type = SR_DF_ANALOG_OLD,
c9404469 DG	344	.payload = &analog,
	345	};
	346	float factor = devc->factor;
	347
	348	while (num--)
	349	data[num] = (buf[num] - 0x80) * factor;
	350
695dc859	351	sr_session_send(sdi, &packet);
c9404469 DG	352	}
	353
	354	static int read_subframe(const struct sr_dev_inst sdi, uint8_t buf)
	355	{
	356	struct dev_context *devc = sdi->priv;
	357	uint8_t sig[3], ctrl;
	358	unsigned int num;
	359	gboolean interleave;
	360
	361	interleave = readout_steps[devc->step].interleave;
	362	ctrl = C1284_NSTROBE;
	363	if ((interleave && devc->adc2) \|\| (!interleave && devc->channel == 2))
	364	ctrl \|= C1284_NAUTOFD;
	365
	366	ieee1284_write_control(sdi->conn, ctrl);
	367	num = readout_steps[devc->step].num;
	368	if (num < 1000)
	369	skip_samples(sdi->conn, ctrl, 1000 - num);
	370	read_samples(sdi->conn, ctrl, buf + (devc->adc2 ? 1 : 0), num,
	371	interleave ? 2 : 1);
	372	read_samples(sdi->conn, ctrl, sig, 3, 1);
	373	if (sig[0] != 0x01 \|\| sig[1] != 0xfe \|\| sig[2] != 0x80) {
	374	if (--devc->retries) {
	375	sr_dbg("Missing signature at end of buffer, %i tries remaining",
	376	devc->retries);
	377	return TRUE;
	378	} else {
	379	sr_err("Failed to read frame without transfer errors");
	380	devc->step = 0;
	381	}
	382	} else {
	383	if (interleave && !devc->adc2) {
	384	devc->adc2 = TRUE;
	385	devc->retries = MAX_RETRIES;
	386	return TRUE;
	387	} else {
	388	if (interleave)
	389	num *= 2;
	390	if (!devc->step) {
	391	struct sr_datafeed_packet packet = {
	392	.type = SR_DF_TRIGGER
	393	};
	394
	395	push_samples(sdi, buf, 6);
695dc859	396	sr_session_send(sdi, &packet);
c9404469 DG	397	buf += 6;
	398	num -= 6;
	399	}
	400	push_samples(sdi, buf, num);
	401	if (++devc->step > devc->last_step)
	402	devc->step = 0;
	403	}
	404	}
	405
	406	devc->adc2 = FALSE;
	407	devc->retries = MAX_RETRIES;
	408
	409	return devc->step > 0;
	410	}
	411
	412	SR_PRIV int hung_chang_dso_2100_poll(int fd, int revents, void *cb_data)
	413	{
	414	struct sr_datafeed_packet packet = { .type = SR_DF_FRAME_BEGIN };
05ac4a98 DG	415	const struct sr_dev_inst *sdi;
05ac4a98 DG	416	struct dev_context *devc;
c9404469	417	uint8_t state, buf[1000];
05ac4a98 DG	418
05ac4a98 DG	419	(void)fd;
c9404469	420	(void)revents;
05ac4a98 DG	421
	422	if (!(sdi = cb_data))
	423	return TRUE;
	424
	425	if (!(devc = sdi->priv))
	426	return TRUE;
	427
c9404469 DG	428	if (devc->state_known)
	429	hung_chang_dso_2100_write_mbox(sdi->conn, 0x99);
	430
	431	state = hung_chang_dso_2100_read_mbox(sdi->conn, 0.00025);
	432	devc->state_known = (state != 0x00);
	433
	434	if (!devc->state_known \|\| state == 0x21)
	435	return TRUE;
	436
	437	if (state != 0x03) {
6433156c	438	sr_err("Unexpected state 0x%X while checking for trigger", state);
c9404469 DG	439	return FALSE;
	440	}
	441
695dc859	442	sr_session_send(sdi, &packet);
c9404469 DG	443
	444	if (devc->channel) {
	445	while (read_subframe(sdi, buf)) {
	446	if (hung_chang_dso_2100_move_to(sdi, 1) != SR_OK)
	447	break;
	448	hung_chang_dso_2100_write_mbox(sdi->conn, 3);
	449	g_usleep(1700);
	450	if (hung_chang_dso_2100_read_mbox(sdi->conn, 0.02) != 0x03)
	451	break;
	452	}
05ac4a98 DG	453	}
05ac4a98 DG	454
c9404469	455	packet.type = SR_DF_FRAME_END;
695dc859	456	sr_session_send(sdi, &packet);
c9404469 DG	457
c9404469 DG	458	if (++devc->frame >= devc->frame_limit)
695dc859	459	hung_chang_dso_2100_dev_acquisition_stop(sdi);
c9404469 DG	460	else
	461	hung_chang_dso_2100_move_to(sdi, 0x21);
	462
05ac4a98 DG	463	return TRUE;
05ac4a98 DG	464	}