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05ac4a98 DG |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2015 Daniel Glöckner <daniel-gl@gmx.net> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
c9404469 | 20 | #include <ieee1284.h> |
05ac4a98 DG |
21 | #include "protocol.h" |
22 | ||
c9404469 DG |
23 | /* The firmware can be in the following states: |
24 | * 0x00 Temporary state during initialization | |
25 | * Automatically transitions to state 0x01 | |
26 | * 0x01 Idle, this state updates calibration caps | |
27 | * Send 0x02 to go to state 0x21 | |
28 | * Send 0x03 to go to state 0x03 | |
29 | * Send 0x04 to go to state 0x14 | |
30 | * 0x21 Trigger is armed, caps are _not_ updated | |
31 | * Send 0x99 to check if trigger event occured | |
32 | * if triggered, goes to state 0x03 | |
33 | * else stays in state 0x21 | |
34 | * Send 0xFE to generate artificial trigger event | |
35 | * returns to state 0x21 | |
36 | * but next 0x99 will succeed | |
37 | * Send 0xFF to go to state 0x03 (abort capture) | |
38 | * 0x03 Extracts two 500 sample subsets from the 5000 | |
39 | * sample capture buffer for readout | |
40 | * When reading samples, the FPGA starts at the | |
41 | * first of the 1000 samples and automatically | |
42 | * advances to the next. | |
43 | * Send 0x04 to go to state 0x0F | |
44 | * 0x14 Scroll acquisition mode, update calib caps | |
45 | * When reading samples, the FPGA provides the | |
46 | * current value of the ADCs | |
47 | * Send 0xFF to go to state 0x0F | |
48 | * 0x0F Send channel number (1 or 2) to go to next state | |
49 | * There are actually two 0x0F states in series | |
50 | * which both expect the channel number. | |
51 | * If the values don't match, they are discarded. | |
52 | * The next state 0x05 is entered anyway | |
53 | * 0x05 Same as state 0x0F but expects sample rate index. | |
54 | * The next state is 0x08 | |
55 | * 0x08 Same as state 0x0F but expects step size + 1 for | |
56 | * the second 500 sample subset | |
57 | * The next state is 0x09 | |
58 | * 0x09 Same as state 0x0F but expects step size + 1 for | |
59 | * the first 500 sample subset | |
60 | * The next state is 0x06 | |
61 | * 0x06 Same as state 0x0F but expects vdiv and coupling | |
62 | * configuration for the first channel and trigger | |
63 | * source selection. | |
64 | * (U46 in the schematics) | |
65 | * The next state is 0x07 | |
66 | * 0x07 Same as state 0x0F but expects vdiv and coupling | |
67 | * configuration for the first channel and trigger | |
68 | * type (edge, TV hsync, TV vsync). | |
69 | * (U47 in the schematics) | |
70 | * The next state is 0x0A | |
71 | * 0x0A Same as state 0x0F but expects a parameter X + 1 | |
72 | * that determines the offset of the second 500 sample | |
73 | * subset | |
74 | * Offset = 5 * X * step size for first subset | |
75 | * The next state is 0x0B | |
76 | * 0x0B Same as state 0x0F but expects the type of edge to | |
77 | * trigger on (rising or falling) | |
78 | * The next state is 0x0C | |
79 | * 0x0C Same as state 0x0F but expects the calibration | |
80 | * value for the first channel's position | |
81 | * (POS1 in the schematics) | |
82 | * The next state is 0x0D | |
83 | * 0x0D Same as state 0x0F but expects the calibration | |
84 | * value for the second channel's position | |
85 | * (POS2 in the schematics) | |
86 | * The next state is 0x0E | |
87 | * 0x0E Same as state 0x0F but expects the trigger level | |
88 | * (TRIGLEVEL in the schematics) | |
89 | * Keep in mind that trigger sources are AC coupled | |
90 | * The next state is 0x10 | |
91 | * 0x10 Same as state 0x0F but expects the calibration | |
92 | * value for the first channel's offset | |
93 | * (OFFSET1 in the schematics) | |
94 | * The next state is 0x11 | |
95 | * 0x11 Same as state 0x0F but expects the calibration | |
96 | * value for the first channel's gain | |
97 | * (GAIN1 in the schematics) | |
98 | * The next state is 0x12 | |
99 | * 0x12 Same as state 0x0F but expects the calibration | |
100 | * value for the second channel's offset | |
101 | * (OFFSET2 in the schematics) | |
102 | * The next state is 0x13 | |
103 | * 0x13 Same as state 0x0F but expects the calibration | |
104 | * value for the second channel's gain | |
105 | * (GAIN2 in the schematics) | |
106 | * The next state is 0x01 | |
107 | * | |
108 | * The Mailbox appears to be half duplex. | |
109 | * If one side writes a byte into the mailbox, it | |
110 | * reads 0 until the other side has written a byte. | |
111 | * So you can't transfer 0. | |
112 | * | |
113 | * As the status signals are unconnected, the device is not | |
114 | * IEEE1284 compliant and can't make use of EPP or ECP transfers. | |
115 | * It drives the data lines when control is set to: | |
116 | * 0 => Channel A data | |
117 | * C1284_NAUTOFD => Channel B data | |
118 | * C1284_NSELECTIN => Mailbox | |
119 | * C1284_NSELECTIN | C1284_NAUTOFD => 0x55 | |
120 | * | |
121 | * It takes about 200ns for the data lines to become stable after | |
122 | * the control lines have been changed. This driver assumes that | |
123 | * parallel port access is slow enough to not require additional | |
124 | * delays. | |
125 | * | |
126 | * Channel values in state 0x14 and the mailbox can change their | |
127 | * value while they are selected, the latter of course only from | |
128 | * 0 to a valid state. Beware of intermediate values. | |
129 | * | |
130 | * SRAM N layout (N = 1 or 2): | |
131 | * 0x0000-0x13ff samples captured from ADC N | |
132 | * 0x4000-0x41f3 bytes extracted from 0x6000 with step1 | |
133 | * (both ADCs but only channel N) | |
134 | * 0x41f4-0x43e7 bytes extracted from 0x6000+5*step1*shift | |
135 | * with step2 (both ADCs but only channel N) | |
136 | * 0x43e8-0x43ea {0x01, 0xfe, 0x80} | |
137 | * 0x43eb-0x444e copy of bytes from 0x4320 | |
138 | * 0x6000-0x7387 interleaved SRAM 1 and SRAM 2 bytes from | |
139 | * 0x0001 to 0x09c5 after channel N was captured | |
140 | * | |
141 | * On a trigger event the FPGA directs the ADC samples to the region | |
142 | * at 0x0000. The microcontroller then copies 5000 samples from 0x0001 | |
143 | * to 0x6000. Each time state 0x03 is entered, the bytes from 0x4000 | |
144 | * to 0x444e are filled and the start address for readout is reset to | |
145 | * 0x4000. Readout will wrap around back to 0x4000 after reaching 0x7fff. | |
146 | * | |
147 | * As you can see from the layout, it was probably intended to capture | |
148 | * 5000 samples for both probes before they are read out. We don't do that | |
149 | * to be able to read the full 10k samples captured by the FPGA. It would | |
150 | * be useless anyway if you don't capture repetitive signals. We're also | |
151 | * not reading the two samples at 0x0000 to save a few milliseconds. | |
152 | */ | |
153 | ||
154 | static const struct { | |
155 | uint16_t num; | |
156 | uint8_t step1; | |
157 | uint8_t shift; | |
158 | uint8_t interleave; | |
159 | } readout_steps[] = { | |
160 | { 1000, 1, 100, 0 }, | |
161 | { 500, 100, 2, 0 }, | |
162 | { 500, 100, 3, 0 }, | |
163 | { 500, 100, 4, 0 }, | |
164 | { 500, 100, 5, 0 }, | |
165 | { 500, 100, 6, 0 }, | |
166 | { 500, 100, 7, 0 }, | |
167 | { 500, 100, 8, 0 }, | |
168 | { 500, 100, 9, 0 }, | |
169 | { 499, 212, 41, 1 }, | |
170 | { 500, 157, 56, 1 }, | |
171 | { 500, 247, 36, 1 }, | |
172 | { 500, 232, 180, 1 }, | |
173 | { 500, 230, 182, 1 }, | |
174 | { 120, 212, 43, 1 } | |
175 | }; | |
176 | ||
177 | SR_PRIV void hung_chang_dso_2100_reset_port(struct parport *port) | |
05ac4a98 | 178 | { |
c9404469 DG |
179 | ieee1284_write_control(port, |
180 | C1284_NSTROBE | C1284_NAUTOFD | C1284_NSELECTIN); | |
181 | ieee1284_data_dir(port, 0); | |
182 | } | |
183 | ||
184 | SR_PRIV gboolean hung_chang_dso_2100_check_id(struct parport *port) | |
185 | { | |
186 | gboolean ret = FALSE; | |
187 | ||
188 | if (ieee1284_data_dir(port, 1) != E1284_OK) | |
189 | goto fail; | |
190 | ||
191 | ieee1284_write_control(port, C1284_NSTROBE | C1284_NAUTOFD | C1284_NSELECTIN); | |
192 | ieee1284_write_control(port, C1284_NAUTOFD | C1284_NSELECTIN); | |
193 | ||
194 | if (ieee1284_read_data(port) != 0x55) | |
195 | goto fail; | |
196 | ||
197 | ret = TRUE; | |
198 | fail: | |
199 | hung_chang_dso_2100_reset_port(port); | |
200 | ||
201 | return ret; | |
202 | } | |
203 | ||
204 | SR_PRIV void hung_chang_dso_2100_write_mbox(struct parport *port, uint8_t val) | |
205 | { | |
206 | sr_dbg("mbox <= %X", val); | |
207 | ieee1284_write_control(port, | |
208 | C1284_NSTROBE | C1284_NINIT | C1284_NSELECTIN); | |
209 | ieee1284_data_dir(port, 0); | |
210 | ieee1284_write_data(port, val); | |
211 | ieee1284_write_control(port, C1284_NINIT | C1284_NSELECTIN); | |
212 | ieee1284_write_control(port, | |
213 | C1284_NSTROBE | C1284_NINIT | C1284_NSELECTIN); | |
214 | ieee1284_data_dir(port, 1); | |
215 | ieee1284_write_control(port, | |
216 | C1284_NSTROBE | C1284_NAUTOFD | C1284_NINIT | C1284_NSELECTIN); | |
217 | } | |
218 | ||
219 | SR_PRIV uint8_t hung_chang_dso_2100_read_mbox(struct parport *port, float timeout) | |
220 | { | |
221 | GTimer *timer = NULL; | |
222 | uint8_t val; | |
223 | ||
224 | ieee1284_write_control(port, C1284_NSTROBE | C1284_NSELECTIN); | |
225 | ieee1284_write_control(port, C1284_NSELECTIN); | |
226 | ||
227 | for (;;) { | |
228 | if (ieee1284_read_data(port)) { | |
229 | /* Always read the value a second time. | |
230 | * The first one may be unstable. */ | |
231 | val = ieee1284_read_data(port); | |
232 | break; | |
233 | } | |
234 | if (!timer) { | |
235 | timer = g_timer_new(); | |
236 | } else if (g_timer_elapsed(timer, NULL) > timeout) { | |
237 | val = 0; | |
238 | break; | |
239 | } | |
240 | } | |
241 | ||
242 | ieee1284_write_control(port, C1284_NSTROBE | C1284_NSELECTIN); | |
243 | ieee1284_write_control(port, | |
244 | C1284_NSTROBE | C1284_NAUTOFD | C1284_NINIT | C1284_NSELECTIN); | |
245 | ||
246 | if (timer) | |
247 | g_timer_destroy(timer); | |
248 | sr_dbg("mbox == %X", val); | |
249 | return val; | |
250 | } | |
251 | ||
252 | SR_PRIV int hung_chang_dso_2100_move_to(const struct sr_dev_inst *sdi, uint8_t target) | |
253 | { | |
254 | struct dev_context *devc = sdi->priv; | |
255 | int timeout = 40; | |
256 | uint8_t c; | |
257 | ||
258 | while (timeout--) { | |
259 | c = hung_chang_dso_2100_read_mbox(sdi->conn, 0.1); | |
260 | if (c == target) | |
261 | return SR_OK; | |
262 | ||
263 | switch (c) { | |
264 | case 0x00: | |
265 | /* Can happen if someone wrote something into | |
266 | * the mbox that was not expected by the uC. | |
267 | * Alternating between 0xff and 4 helps in | |
268 | * all states. */ | |
269 | c = (timeout & 1) ? 0xFF : 0x04; | |
270 | break; | |
271 | case 0x01: | |
272 | switch (target) { | |
273 | case 0x21: c = 2; break; | |
274 | case 0x03: c = 3; break; | |
275 | default: c = 4; | |
276 | } | |
277 | break; | |
278 | case 0x03: c = 4; break; | |
279 | case 0x05: c = devc->rate + 1; break; | |
280 | case 0x06: c = devc->cctl[0]; break; | |
281 | case 0x07: c = devc->cctl[1]; break; | |
282 | case 0x08: c = 1 /* step 2 */ + 1 ; break; | |
283 | case 0x09: c = readout_steps[devc->step].step1 + 1; break; | |
284 | case 0x0A: c = readout_steps[devc->step].shift + 1; break; | |
285 | case 0x0B: c = devc->edge + 1; break; | |
286 | case 0x0C: c = devc->pos[0]; break; | |
287 | case 0x0D: c = devc->pos[1]; break; | |
288 | case 0x0E: c = devc->tlevel; break; | |
289 | case 0x0F: | |
290 | if (!devc->channel) | |
291 | c = 1; | |
292 | else if (readout_steps[devc->step].interleave) | |
293 | c = devc->adc2 ? 2 : 1; | |
294 | else | |
295 | c = devc->channel; | |
296 | break; | |
297 | case 0x10: c = devc->offset[0]; break; | |
298 | case 0x11: c = devc->gain[0]; break; | |
299 | case 0x12: c = devc->offset[1]; break; | |
300 | case 0x13: c = devc->gain[1]; break; | |
301 | case 0x14: | |
302 | case 0x21: c = 0xFF; break; | |
303 | default: | |
304 | return SR_ERR_DATA; | |
305 | } | |
306 | hung_chang_dso_2100_write_mbox(sdi->conn, c); | |
307 | } | |
308 | return SR_ERR_TIMEOUT; | |
309 | } | |
310 | ||
311 | static void skip_samples(struct parport *port, uint8_t ctrl, size_t num) | |
312 | { | |
313 | while (num--) { | |
314 | ieee1284_write_control(port, ctrl & ~C1284_NSTROBE); | |
315 | ieee1284_write_control(port, ctrl); | |
316 | } | |
317 | } | |
318 | ||
319 | static void read_samples(struct parport *port, uint8_t ctrl, uint8_t *buf, size_t num, size_t stride) | |
320 | { | |
321 | while (num--) { | |
322 | ieee1284_write_control(port, ctrl & ~C1284_NSTROBE); | |
323 | *buf = ieee1284_read_data(port); | |
324 | buf += stride; | |
325 | ieee1284_write_control(port, ctrl); | |
326 | } | |
327 | } | |
328 | ||
329 | static void push_samples(const struct sr_dev_inst *sdi, uint8_t *buf, size_t num) | |
330 | { | |
331 | struct dev_context *devc = sdi->priv; | |
332 | float *data = devc->samples; | |
333 | struct sr_datafeed_analog analog = { | |
334 | .channels = devc->enabled_channel, | |
335 | .num_samples = num, | |
336 | .mq = SR_MQ_VOLTAGE, | |
337 | .unit = SR_UNIT_VOLT, | |
338 | .mqflags = 0, | |
339 | .data = data, | |
340 | }; | |
341 | struct sr_datafeed_packet packet = { | |
342 | .type = SR_DF_ANALOG, | |
343 | .payload = &analog, | |
344 | }; | |
345 | float factor = devc->factor; | |
346 | ||
347 | while (num--) | |
348 | data[num] = (buf[num] - 0x80) * factor; | |
349 | ||
350 | sr_session_send(devc->cb_data, &packet); | |
351 | } | |
352 | ||
353 | static int read_subframe(const struct sr_dev_inst *sdi, uint8_t *buf) | |
354 | { | |
355 | struct dev_context *devc = sdi->priv; | |
356 | uint8_t sig[3], ctrl; | |
357 | unsigned int num; | |
358 | gboolean interleave; | |
359 | ||
360 | interleave = readout_steps[devc->step].interleave; | |
361 | ctrl = C1284_NSTROBE; | |
362 | if ((interleave && devc->adc2) || (!interleave && devc->channel == 2)) | |
363 | ctrl |= C1284_NAUTOFD; | |
364 | ||
365 | ieee1284_write_control(sdi->conn, ctrl); | |
366 | num = readout_steps[devc->step].num; | |
367 | if (num < 1000) | |
368 | skip_samples(sdi->conn, ctrl, 1000 - num); | |
369 | read_samples(sdi->conn, ctrl, buf + (devc->adc2 ? 1 : 0), num, | |
370 | interleave ? 2 : 1); | |
371 | read_samples(sdi->conn, ctrl, sig, 3, 1); | |
372 | if (sig[0] != 0x01 || sig[1] != 0xfe || sig[2] != 0x80) { | |
373 | if (--devc->retries) { | |
374 | sr_dbg("Missing signature at end of buffer, %i tries remaining", | |
375 | devc->retries); | |
376 | return TRUE; | |
377 | } else { | |
378 | sr_err("Failed to read frame without transfer errors"); | |
379 | devc->step = 0; | |
380 | } | |
381 | } else { | |
382 | if (interleave && !devc->adc2) { | |
383 | devc->adc2 = TRUE; | |
384 | devc->retries = MAX_RETRIES; | |
385 | return TRUE; | |
386 | } else { | |
387 | if (interleave) | |
388 | num *= 2; | |
389 | if (!devc->step) { | |
390 | struct sr_datafeed_packet packet = { | |
391 | .type = SR_DF_TRIGGER | |
392 | }; | |
393 | ||
394 | push_samples(sdi, buf, 6); | |
395 | sr_session_send(devc->cb_data, &packet); | |
396 | buf += 6; | |
397 | num -= 6; | |
398 | } | |
399 | push_samples(sdi, buf, num); | |
400 | if (++devc->step > devc->last_step) | |
401 | devc->step = 0; | |
402 | } | |
403 | } | |
404 | ||
405 | devc->adc2 = FALSE; | |
406 | devc->retries = MAX_RETRIES; | |
407 | ||
408 | return devc->step > 0; | |
409 | } | |
410 | ||
411 | SR_PRIV int hung_chang_dso_2100_poll(int fd, int revents, void *cb_data) | |
412 | { | |
413 | struct sr_datafeed_packet packet = { .type = SR_DF_FRAME_BEGIN }; | |
05ac4a98 DG |
414 | const struct sr_dev_inst *sdi; |
415 | struct dev_context *devc; | |
c9404469 | 416 | uint8_t state, buf[1000]; |
05ac4a98 DG |
417 | |
418 | (void)fd; | |
c9404469 | 419 | (void)revents; |
05ac4a98 DG |
420 | |
421 | if (!(sdi = cb_data)) | |
422 | return TRUE; | |
423 | ||
424 | if (!(devc = sdi->priv)) | |
425 | return TRUE; | |
426 | ||
c9404469 DG |
427 | if (devc->state_known) |
428 | hung_chang_dso_2100_write_mbox(sdi->conn, 0x99); | |
429 | ||
430 | state = hung_chang_dso_2100_read_mbox(sdi->conn, 0.00025); | |
431 | devc->state_known = (state != 0x00); | |
432 | ||
433 | if (!devc->state_known || state == 0x21) | |
434 | return TRUE; | |
435 | ||
436 | if (state != 0x03) { | |
437 | sr_err("Unexpected state 0x%X while checking for trigger"); | |
438 | return FALSE; | |
439 | } | |
440 | ||
441 | sr_session_send(devc->cb_data, &packet); | |
442 | ||
443 | if (devc->channel) { | |
444 | while (read_subframe(sdi, buf)) { | |
445 | if (hung_chang_dso_2100_move_to(sdi, 1) != SR_OK) | |
446 | break; | |
447 | hung_chang_dso_2100_write_mbox(sdi->conn, 3); | |
448 | g_usleep(1700); | |
449 | if (hung_chang_dso_2100_read_mbox(sdi->conn, 0.02) != 0x03) | |
450 | break; | |
451 | } | |
05ac4a98 DG |
452 | } |
453 | ||
c9404469 DG |
454 | packet.type = SR_DF_FRAME_END; |
455 | sr_session_send(devc->cb_data, &packet); | |
456 | ||
457 | if (++devc->frame >= devc->frame_limit) | |
458 | hung_chang_dso_2100_dev_acquisition_stop(sdi, devc->cb_data); | |
459 | else | |
460 | hung_chang_dso_2100_move_to(sdi, 0x21); | |
461 | ||
05ac4a98 DG |
462 | return TRUE; |
463 | } |