def reduce_bus(bus):
if 0xFF in bus:
- return None # unassigned bus probes
+ return None # unassigned bus channels
else:
return reduce(lambda a, b: (a << 1) | b, reversed(bus))
return byte if byte < 128 else byte - 256
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 3
id = 'z80'
name = 'Z80'
longname = 'Zilog Z80 CPU'
desc = 'Zilog Z80 microprocessor disassembly.'
- license = 'gplv2+'
+ license = 'gplv3+'
inputs = ['logic']
- outputs = ['z80']
- probes = tuple({
+ outputs = []
+ tags = ['Retro computing']
+ channels = tuple({
'id': 'd%d' % i,
'name': 'D%d' % i,
'desc': 'Data bus line %d' % i
{'id': 'rd', 'name': '/RD', 'desc': 'Memory or I/O read'},
{'id': 'wr', 'name': '/WR', 'desc': 'Memory or I/O write'},
)
- optional_probes = (
+ optional_channels = (
{'id': 'mreq', 'name': '/MREQ', 'desc': 'Memory request'},
{'id': 'iorq', 'name': '/IORQ', 'desc': 'I/O request'},
) + tuple({
('warnings', 'Warnings', (Ann.WARN,))
)
- def __init__(self, **kwargs):
+ def __init__(self):
+ self.reset()
+
+ def reset(self):
self.prev_cycle = Cycle.NONE
self.op_state = self.state_IDLE
self.op_state = self.state_IDLE
self.instr_len = 0
- def decode(self, ss, es, data):
- for (self.samplenum, pins) in data:
+ def decode(self):
+ while True:
+ # TODO: Come up with more appropriate self.wait() conditions.
+ pins = self.wait()
cycle = Cycle.NONE
if pins[Pin.MREQ] != 1: # default to asserted
if pins[Pin.RD] == 0: