def reduce_bus(bus):
if 0xFF in bus:
- return None # unassigned bus probes
+ return None # unassigned bus channels
else:
return reduce(lambda a, b: (a << 1) | b, reversed(bus))
return byte if byte < 128 else byte - 256
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 3
id = 'z80'
name = 'Z80'
longname = 'Zilog Z80 CPU'
desc = 'Zilog Z80 microprocessor disassembly.'
- license = 'gplv2+'
+ license = 'gplv3+'
inputs = ['logic']
- outputs = ['z80']
- probes = [
- {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data bus line %d' % i}
- for i in range(8)
- ] + [
+ outputs = []
+ tags = ['Retro computing']
+ channels = tuple({
+ 'id': 'd%d' % i,
+ 'name': 'D%d' % i,
+ 'desc': 'Data bus line %d' % i
+ } for i in range(8)
+ ) + (
{'id': 'm1', 'name': '/M1', 'desc': 'Machine cycle 1'},
{'id': 'rd', 'name': '/RD', 'desc': 'Memory or I/O read'},
{'id': 'wr', 'name': '/WR', 'desc': 'Memory or I/O write'},
- ]
- optional_probes = [
+ )
+ optional_channels = (
{'id': 'mreq', 'name': '/MREQ', 'desc': 'Memory request'},
{'id': 'iorq', 'name': '/IORQ', 'desc': 'I/O request'},
- ] + [
- {'id': 'a%d' % i, 'name': 'A%d' % i, 'desc': 'Address bus line %d' % i}
- for i in range(16)
- ]
- options = {}
- annotations = [
- ['addr', 'Memory or I/O address'],
- ['memrd', 'Byte read from memory'],
- ['memwr', 'Byte written to memory'],
- ['iord', 'Byte read from I/O port'],
- ['iowr', 'Byte written to I/O port'],
- ['instr', 'Z80 CPU instruction'],
- ['rop', 'Value of input operand'],
- ['wop', 'Value of output operand'],
- ['warn', 'Warning message'],
- ]
+ ) + tuple({
+ 'id': 'a%d' % i,
+ 'name': 'A%d' % i,
+ 'desc': 'Address bus line %d' % i
+ } for i in range(16)
+ )
+ annotations = (
+ ('addr', 'Memory or I/O address'),
+ ('memrd', 'Byte read from memory'),
+ ('memwr', 'Byte written to memory'),
+ ('iord', 'Byte read from I/O port'),
+ ('iowr', 'Byte written to I/O port'),
+ ('instr', 'Z80 CPU instruction'),
+ ('rop', 'Value of input operand'),
+ ('wop', 'Value of output operand'),
+ ('warn', 'Warning message'),
+ )
annotation_rows = (
('addrbus', 'Address bus', (Ann.ADDR,)),
('databus', 'Data bus', (Ann.MEMRD, Ann.MEMWR, Ann.IORD, Ann.IOWR)),
('warnings', 'Warnings', (Ann.WARN,))
)
- def __init__(self, **kwargs):
+ def __init__(self):
+ self.reset()
+
+ def reset(self):
self.prev_cycle = Cycle.NONE
self.op_state = self.state_IDLE
self.op_state = self.state_IDLE
self.instr_len = 0
- def decode(self, ss, es, data):
- for (self.samplenum, pins) in data:
+ def decode(self):
+ while True:
+ # TODO: Come up with more appropriate self.wait() conditions.
+ pins = self.wait()
cycle = Cycle.NONE
if pins[Pin.MREQ] != 1: # default to asserted
if pins[Pin.RD] == 0: