## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# USB signalling (low-speed and full-speed) protocol decoder
-
import sigrokdecode as srd
+'''
+OUTPUT_PYTHON format:
+
+Packet:
+[<ptype>, <pdata>]
+
+<ptype>, <pdata>:
+ - 'SOP', None
+ - 'SYM', <sym>
+ - 'BIT', <bit>
+ - 'STUFF BIT', None
+ - 'EOP', None
+
+<sym>:
+ - 'J', 'K', 'SE0', or 'SE1'
+
+<bit>:
+ - 0 or 1
+ - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
+'''
+
# Low-/full-speed symbols.
# Note: Low-speed J and K are inverted compared to the full-speed J and K!
symbols = {
'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
}
+sym_idx = {
+ 'J': 0,
+ 'K': 1,
+ 'SE0': 2,
+ 'SE1': 3,
+}
+
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 2
id = 'usb_signalling'
name = 'USB signalling'
longname = 'Universal Serial Bus (LS/FS) signalling'
license = 'gplv2+'
inputs = ['logic']
outputs = ['usb_signalling']
- probes = [
+ channels = (
{'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
{'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
- ]
- optional_probes = []
- options = {
- 'signalling': ['Signalling', 'full-speed'],
- }
- annotations = [
- ['Text', 'Human-readable text'],
- ]
+ )
+ options = (
+ {'id': 'signalling', 'desc': 'Signalling',
+ 'default': 'full-speed', 'values': ('full-speed', 'low-speed')},
+ )
+ annotations = (
+ ('sym-j', 'J symbol'),
+ ('sym-k', 'K symbol'),
+ ('sym-se0', 'SE0 symbol'),
+ ('sym-se1', 'SE1 symbol'),
+ ('sop', 'Start of packet (SOP)'),
+ ('eop', 'End of packet (EOP)'),
+ ('bit', 'Bit'),
+ ('stuffbit', 'Stuff bit'),
+ )
+ annotation_rows = (
+ ('bits', 'Bits', (4, 5, 6, 7)),
+ ('symbols', 'Symbols', (0, 1, 2, 3)),
+ )
def __init__(self):
+ self.samplerate = None
self.oldsym = 'J' # The "idle" state is J.
- self.ss_sop = -1
+ self.ss_sop = None
+ self.ss_block = None
self.samplenum = 0
- self.packet = ''
self.syms = []
self.bitrate = None
self.bitwidth = None
self.consecutive_ones = 0
self.state = 'IDLE'
- def start(self, metadata):
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling')
- self.bitrate = bitrates[self.options['signalling']]
- self.bitwidth = float(metadata['samplerate']) / float(self.bitrate)
+ def start(self):
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
- def report(self):
- pass
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value
+ self.bitrate = bitrates[self.options['signalling']]
+ self.bitwidth = float(self.samplerate) / float(self.bitrate)
+ self.halfbit = int(self.bitwidth / 2)
def putpx(self, data):
- self.put(self.samplenum, self.samplenum, self.out_proto, data)
+ self.put(self.samplenum, self.samplenum, self.out_python, data)
def putx(self, data):
self.put(self.samplenum, self.samplenum, self.out_ann, data)
+ def putpm(self, data):
+ s, h = self.samplenum, self.halfbit
+ self.put(self.ss_block - h, s + h, self.out_python, data)
+
+ def putm(self, data):
+ s, h = self.samplenum, self.halfbit
+ self.put(self.ss_block - h, s + h, self.out_ann, data)
+
def putpb(self, data):
- s, halfbit = self.samplenum, int(self.bitwidth / 2)
- self.put(s - halfbit, s + halfbit, self.out_proto, data)
+ s, h = self.samplenum, self.halfbit
+ self.put(s - h, s + h, self.out_python, data)
def putb(self, data):
- s, halfbit = self.samplenum, int(self.bitwidth / 2)
- self.put(s - halfbit, s + halfbit, self.out_ann, data)
+ s, h = self.samplenum, self.halfbit
+ self.put(s - h, s + h, self.out_ann, data)
def set_new_target_samplenum(self):
bitpos = self.ss_sop + (self.bitwidth / 2)
self.ss_sop = self.samplenum
self.set_new_target_samplenum()
self.putpx(['SOP', None])
- self.putx([0, ['SOP']])
+ self.putx([4, ['SOP', 'S']])
self.state = 'GET BIT'
def handle_bit(self, sym, b):
if self.consecutive_ones == 6 and b == '0':
- # Stuff bit. Don't add to the packet, reset self.consecutive_ones.
- self.putb([0, ['SB: %s/%s' % (sym, b)]])
+ # Stuff bit.
+ self.putpb(['STUFF BIT', None])
+ self.putb([7, ['Stuff bit: %s' % b, 'SB: %s' % b, '%s' % b]])
+ self.putb([sym_idx[sym], ['%s' % sym]])
self.consecutive_ones = 0
else:
- # Normal bit. Add it to the packet, update self.consecutive_ones.
- self.putb([0, ['%s/%s' % (sym, b)]])
- self.packet += b
+ # Normal bit (not a stuff bit).
+ self.putpb(['BIT', b])
+ self.putb([6, ['%s' % b]])
+ self.putb([sym_idx[sym], ['%s' % sym]])
if b == '1':
self.consecutive_ones += 1
else:
# EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
self.syms.append(sym)
self.putpb(['SYM', sym])
- self.putb([0, ['%s' % sym]])
+ self.putb([sym_idx[sym], ['%s' % sym, '%s' % sym[0]]])
self.bitnum += 1
self.set_new_target_samplenum()
self.oldsym = sym
if self.syms[-2:] == ['SE0', 'J']:
- # Got an EOP, i.e. we now have a full packet.
- self.putpb(['PACKET', self.packet])
- self.putb([0, ['PACKET: %s' % self.packet]])
- self.bitnum, self.packet, self.syms, self.state = 0, '', [], 'IDLE'
+ # Got an EOP.
+ self.putpm(['EOP', None])
+ self.putm([5, ['EOP', 'E']])
+ self.bitnum, self.syms, self.state = 0, [], 'IDLE'
self.consecutive_ones = 0
def get_bit(self, sym):
if sym == 'SE0':
# Start of an EOP. Change state, run get_eop() for this bit.
self.state = 'GET EOP'
+ self.ss_block = self.samplenum
self.get_eop(sym)
return
self.syms.append(sym)
self.oldsym = sym
def decode(self, ss, es, data):
+ if self.samplerate is None:
+ raise Exception("Cannot decode without samplerate.")
for (self.samplenum, pins) in data:
# State machine.
if self.state == 'IDLE':