## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# USB signalling (low-speed and full-speed) protocol decoder
-
import sigrokdecode as srd
'''
-Protocol output format:
+OUTPUT_PYTHON format:
Packet:
[<ptype>, <pdata>]
license = 'gplv2+'
inputs = ['logic']
outputs = ['usb_signalling']
- probes = [
+ probes = (
{'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
{'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
- ]
- optional_probes = []
- options = {
- 'signalling': ['Signalling', 'full-speed'],
- }
- annotations = [
- ['sym', 'Symbol'],
- ['sop', 'Start of packet (SOP)'],
- ['eop', 'End of packet (EOP)'],
- ['bit', 'Bit'],
- ['stuffbit', 'Stuff bit'],
- ]
+ )
+ options = (
+ {'id': 'signalling', 'desc': 'Signalling',
+ 'default': 'full-speed', 'values': ('full-speed', 'low-speed')},
+ )
+ annotations = (
+ ('sym', 'Symbol'),
+ ('sop', 'Start of packet (SOP)'),
+ ('eop', 'End of packet (EOP)'),
+ ('bit', 'Bit'),
+ ('stuffbit', 'Stuff bit'),
+ )
+ annotation_rows = (
+ ('bits', 'Bits', (1, 2, 3, 4)),
+ ('symbols', 'Symbols', (0,)),
+ )
def __init__(self):
self.samplerate = None
self.state = 'IDLE'
def start(self):
- self.out_proto = self.register(srd.OUTPUT_PYTHON)
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
def metadata(self, key, value):
self.halfbit = int(self.bitwidth / 2)
def putpx(self, data):
- self.put(self.samplenum, self.samplenum, self.out_proto, data)
+ self.put(self.samplenum, self.samplenum, self.out_python, data)
def putx(self, data):
self.put(self.samplenum, self.samplenum, self.out_ann, data)
def putpm(self, data):
s, h = self.samplenum, self.halfbit
- self.put(self.ss_block - h, s + h, self.out_proto, data)
+ self.put(self.ss_block - h, s + h, self.out_python, data)
def putm(self, data):
s, h = self.samplenum, self.halfbit
def putpb(self, data):
s, h = self.samplenum, self.halfbit
- self.put(s - h, s + h, self.out_proto, data)
+ self.put(s - h, s + h, self.out_python, data)
def putb(self, data):
s, h = self.samplenum, self.halfbit
if self.consecutive_ones == 6 and b == '0':
# Stuff bit.
self.putpb(['STUFF BIT', None])
- self.putb([4, ['SB: %s/%s' % (sym, b)]])
+ self.putb([4, ['SB: %s' % b]])
+ self.putb([0, ['%s' % sym]])
self.consecutive_ones = 0
else:
# Normal bit (not a stuff bit).
self.putpb(['BIT', b])
- self.putb([3, ['%s/%s' % (sym, b)]])
+ self.putb([3, ['%s' % b]])
+ self.putb([0, ['%s' % sym]])
if b == '1':
self.consecutive_ones += 1
else: