##
import sigrokdecode as srd
+from common.srdhelper import bitpack
from math import floor, ceil
'''
self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data)
def __init__(self):
+ self.reset()
+
+ def reset(self):
self.samplerate = None
self.samplenum = 0
self.frame_start = [-1, -1]
self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
def get_sample_point(self, rxtx, bitnum):
- """Determine absolute sample number of a bit slot's sample point."""
+ # Determine absolute sample number of a bit slot's sample point.
# bitpos is the samplenumber which is in the middle of the
# specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
# (if used) or the first stop bit, and so on).
self.datavalue[rxtx] = 0
self.startsample[rxtx] = -1
- self.state[rxtx] = 'GET DATA BITS'
-
self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
+ self.state[rxtx] = 'GET DATA BITS'
+
def get_data_bits(self, rxtx, signal):
# Save the sample number of the middle of the first data bit.
if self.startsample[rxtx] == -1:
self.startsample[rxtx] = self.samplenum
- # Get the next data bit in LSB-first or MSB-first fashion.
- if self.options['bit_order'] == 'lsb-first':
- self.datavalue[rxtx] >>= 1
- self.datavalue[rxtx] |= \
- (signal << (self.options['num_data_bits'] - 1))
- else:
- self.datavalue[rxtx] <<= 1
- self.datavalue[rxtx] |= (signal << 0)
-
self.putg([rxtx + 12, ['%d' % signal]])
# Store individual data bits and their start/end samplenumbers.
if self.cur_data_bit[rxtx] < self.options['num_data_bits']:
return
- # Skip to either reception of the parity bit, or reception of
- # the STOP bits if parity is not applicable.
- self.state[rxtx] = 'GET PARITY BIT'
- if self.options['parity_type'] == 'none':
- self.state[rxtx] = 'GET STOP BITS'
-
+ # Convert accumulated data bits to a data value.
+ bits = [b[0] for b in self.databits[rxtx]]
+ if self.options['bit_order'] == 'msb-first':
+ bits.reverse()
+ self.datavalue[rxtx] = bitpack(bits)
self.putpx(rxtx, ['DATA', rxtx,
(self.datavalue[rxtx], self.databits[rxtx])])
self.databits[rxtx] = []
+ # Advance to either reception of the parity bit, or reception of
+ # the STOP bits if parity is not applicable.
+ self.state[rxtx] = 'GET PARITY BIT'
+ if self.options['parity_type'] == 'none':
+ self.state[rxtx] = 'GET STOP BITS'
+
def format_value(self, v):
# Format value 'v' according to configured options.
# Reflects the user selected kind of representation, as well as
def get_parity_bit(self, rxtx, signal):
self.paritybit[rxtx] = signal
- self.state[rxtx] = 'GET STOP BITS'
-
if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
self.datavalue[rxtx], self.options['num_data_bits']):
self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
+ self.state[rxtx] = 'GET STOP BITS'
+
# TODO: Currently only supports 1 stop bit.
def get_stop_bits(self, rxtx, signal):
self.stopbit1[rxtx] = signal
self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
# TODO: Abort? Ignore the frame? Other?
- self.state[rxtx] = 'WAIT FOR START BIT'
-
self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
- def get_wait_cond(self, rxtx, inv):
- """
- Determine Decoder.wait() condition for specified UART line.
-
- Returns condititions that are suitable for Decoder.wait(). Those
- conditions either match the falling edge of the START bit, or
- the sample point of the next bit time.
- """
+ self.state[rxtx] = 'WAIT FOR START BIT'
+ def get_wait_cond(self, rxtx, inv):
+ # Return condititions that are suitable for Decoder.wait(). Those
+ # conditions either match the falling edge of the START bit, or
+ # the sample point of the next bit time.
state = self.state[rxtx]
if state == 'WAIT FOR START BIT':
return {rxtx: 'r' if inv else 'f'}
elif state == 'GET STOP BITS':
bitnum = 1 + self.options['num_data_bits']
bitnum += 0 if self.options['parity_type'] == 'none' else 1
- want_num = self.get_sample_point(rxtx, bitnum)
- # want_num = int(want_num + 0.5)
- want_num = ceil(want_num)
- cond = {'skip': want_num - self.samplenum}
- return cond
+ want_num = ceil(self.get_sample_point(rxtx, bitnum))
+ return {'skip': want_num - self.samplenum}
def inspect_sample(self, rxtx, signal, inv):
- """Inspect a sample returned by .wait() for the specified UART line."""
-
+ # Inspect a sample returned by .wait() for the specified UART line.
if inv:
signal = not signal