class ChannelError(Exception):
pass
+class Ann:
+ RX_DATA, TX_DATA, RX_START, TX_START, RX_PARITY_OK, TX_PARITY_OK, \
+ RX_PARITY_ERR, TX_PARITY_ERR, RX_STOP, TX_STOP, RX_WARN, TX_WARN, \
+ RX_DATA_BIT, TX_DATA_BIT, RX_BREAK, TX_BREAK, RX_PACKET, TX_PACKET = \
+ range(18)
+
+class Bin:
+ RX, TX, RXTX = range(3)
+
class Decoder(srd.Decoder):
api_version = 3
id = 'uart'
'values': ('yes', 'no')},
{'id': 'invert_tx', 'desc': 'Invert TX', 'default': 'no',
'values': ('yes', 'no')},
+ {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 50},
{'id': 'rx_packet_delim', 'desc': 'RX packet delimiter (decimal)',
'default': -1},
{'id': 'tx_packet_delim', 'desc': 'TX packet delimiter (decimal)',
annotations = (
('rx-data', 'RX data'),
('tx-data', 'TX data'),
- ('rx-start', 'RX start bits'),
- ('tx-start', 'TX start bits'),
- ('rx-parity-ok', 'RX parity OK bits'),
- ('tx-parity-ok', 'TX parity OK bits'),
- ('rx-parity-err', 'RX parity error bits'),
- ('tx-parity-err', 'TX parity error bits'),
- ('rx-stop', 'RX stop bits'),
- ('tx-stop', 'TX stop bits'),
- ('rx-warnings', 'RX warnings'),
- ('tx-warnings', 'TX warnings'),
- ('rx-data-bits', 'RX data bits'),
- ('tx-data-bits', 'TX data bits'),
+ ('rx-start', 'RX start bit'),
+ ('tx-start', 'TX start bit'),
+ ('rx-parity-ok', 'RX parity OK bit'),
+ ('tx-parity-ok', 'TX parity OK bit'),
+ ('rx-parity-err', 'RX parity error bit'),
+ ('tx-parity-err', 'TX parity error bit'),
+ ('rx-stop', 'RX stop bit'),
+ ('tx-stop', 'TX stop bit'),
+ ('rx-warning', 'RX warning'),
+ ('tx-warning', 'TX warning'),
+ ('rx-data-bit', 'RX data bit'),
+ ('tx-data-bit', 'TX data bit'),
('rx-break', 'RX break'),
('tx-break', 'TX break'),
('rx-packet', 'RX packet'),
('tx-packet', 'TX packet'),
)
annotation_rows = (
- ('rx-data-bits', 'RX bits', (12,)),
- ('rx-data', 'RX', (0, 2, 4, 6, 8)),
- ('rx-warnings', 'RX warnings', (10,)),
- ('rx-break', 'RX break', (14,)),
- ('rx-packets', 'RX packets', (16,)),
- ('tx-data-bits', 'TX bits', (13,)),
- ('tx-data', 'TX', (1, 3, 5, 7, 9)),
- ('tx-warnings', 'TX warnings', (11,)),
- ('tx-break', 'TX break', (15,)),
- ('tx-packets', 'TX packets', (17,)),
+ ('rx-data-bits', 'RX bits', (Ann.RX_DATA_BIT,)),
+ ('rx-data-vals', 'RX data', (Ann.RX_DATA, Ann.RX_START, Ann.RX_PARITY_OK, Ann.RX_PARITY_ERR, Ann.RX_STOP)),
+ ('rx-warnings', 'RX warnings', (Ann.RX_WARN,)),
+ ('rx-breaks', 'RX breaks', (Ann.RX_BREAK,)),
+ ('rx-packets', 'RX packets', (Ann.RX_PACKET,)),
+ ('tx-data-bits', 'TX bits', (Ann.TX_DATA_BIT,)),
+ ('tx-data-vals', 'TX data', (Ann.TX_DATA, Ann.TX_START, Ann.TX_PARITY_OK, Ann.TX_PARITY_ERR, Ann.TX_STOP)),
+ ('tx-warnings', 'TX warnings', (Ann.TX_WARN,)),
+ ('tx-breaks', 'TX breaks', (Ann.TX_BREAK,)),
+ ('tx-packets', 'TX packets', (Ann.TX_PACKET,)),
)
binary = (
('rx', 'RX dump'),
def reset(self):
self.samplerate = None
- self.samplenum = 0
self.frame_start = [-1, -1]
self.frame_valid = [None, None]
self.startbit = [-1, -1]
def get_sample_point(self, rxtx, bitnum):
# Determine absolute sample number of a bit slot's sample point.
- # bitpos is the samplenumber which is in the middle of the
- # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
- # (if used) or the first stop bit, and so on).
- # The samples within bit are 0, 1, ..., (bit_width - 1), therefore
- # index of the middle sample within bit window is (bit_width - 1) / 2.
- bitpos = self.frame_start[rxtx] + (self.bit_width - 1) / 2.0
+ # Counts for UART bits start from 0 (0 = start bit, 1..x = data,
+ # x+1 = parity bit (if used) or the first stop bit, and so on).
+ # Accept a position in the range of 1-99% of the full bit width.
+ # Assume 50% for invalid input specs for backwards compatibility.
+ perc = self.options['sample_point'] or 50
+ if not perc or perc not in range(1, 100):
+ perc = 50
+ perc /= 100.0
+ bitpos = (self.bit_width - 1) * perc
+ bitpos += self.frame_start[rxtx]
bitpos += bitnum * self.bit_width
return bitpos
# for the next start bit (assuming this one was spurious).
if self.startbit[rxtx] != 0:
self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
+ self.putg([Ann.RX_WARN + rxtx, ['Frame error', 'Frame err', 'FE']])
self.frame_valid[rxtx] = False
es = self.samplenum + ceil(self.bit_width / 2.0)
self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx,
self.startsample[rxtx] = -1
self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
+ self.putg([Ann.RX_START + rxtx, ['Start bit', 'Start', 'S']])
self.state[rxtx] = 'GET DATA BITS'
s += ' '
if self.options['format'] != 'ascii' and s[-1] == ' ':
s = s[:-1] # Drop trailing space.
- self.putx_packet(rxtx, [16 + rxtx, [s]])
+ self.putx_packet(rxtx, [Ann.RX_PACKET + rxtx, [s]])
self.packet_cache[rxtx] = []
def get_data_bits(self, rxtx, signal):
if self.startsample[rxtx] == -1:
self.startsample[rxtx] = self.samplenum
- self.putg([rxtx + 12, ['%d' % signal]])
+ self.putg([Ann.RX_DATA_BIT + rxtx, ['%d' % signal]])
# Store individual data bits and their start/end samplenumbers.
s, halfbit = self.samplenum, int(self.bit_width / 2)
self.putx(rxtx, [rxtx, [formatted]])
bdata = b.to_bytes(self.bw, byteorder='big')
- self.putbin(rxtx, [rxtx, bdata])
- self.putbin(rxtx, [2, bdata])
+ self.putbin(rxtx, [Bin.RX + rxtx, bdata])
+ self.putbin(rxtx, [Bin.RXTX, bdata])
self.handle_packet(rxtx)
if parity_ok(self.options['parity'], self.paritybit[rxtx],
self.datavalue[rxtx], self.options['data_bits']):
self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
- self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
+ self.putg([Ann.RX_PARITY_OK + rxtx, ['Parity bit', 'Parity', 'P']])
else:
# TODO: Return expected/actual parity values.
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
- self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
+ self.putg([Ann.RX_PARITY_ERR + rxtx, ['Parity error', 'Parity err', 'PE']])
self.frame_valid[rxtx] = False
self.state[rxtx] = 'GET STOP BITS'
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
+ self.putg([Ann.RX_WARN + rxtx, ['Frame error', 'Frame err', 'FE']])
self.frame_valid[rxtx] = False
self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
+ self.putg([Ann.RX_STOP + rxtx, ['Stop bit', 'Stop', 'T']])
# Pass the complete UART frame to upper layers.
es = self.samplenum + ceil(self.bit_width / 2.0)
self.putpse(self.frame_start[rxtx], self.samplenum,
['BREAK', rxtx, 0])
self.putgse(self.frame_start[rxtx], self.samplenum,
- [rxtx + 14, ['Break condition', 'Break', 'Brk', 'B']])
+ [Ann.RX_BREAK + rxtx, ['Break condition', 'Break', 'Brk', 'B']])
self.state[rxtx] = 'WAIT FOR START BIT'
def get_wait_cond(self, rxtx, inv):