Remove samplerate from srd_decoder_logic_output_channel

[libsigrokdecode.git] / decoders / tca6408a / pd.py

diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py
index 73de1b9f46dd0ef917bd333fc7373ecd3a6731b4..fdfebeddb23d92a26b31a98248993c4b7a405951 100644 (file)
--- a/decoders/tca6408a/pd.py
+++ b/decoders/tca6408a/pd.py
@@ -21,6 +21,14 @@
 
 import sigrokdecode as srd
 
+NUM_OUTPUT_CHANNELS = 8
+
+def logic_channels(num_channels):
+    l = []
+    for i in range(num_channels):
+        l.append(tuple(['p%d' % i, 'P-port input/output %d' % i]))
+    return tuple(l)
+
 class Decoder(srd.Decoder):
     api_version = 3
     id = 'tca6408a'
@@ -29,32 +37,47 @@ class Decoder(srd.Decoder):
     desc = 'Texas Instruments TCA6408A 8-bit I²C I/O expander.'
     license = 'gplv2+'
     inputs = ['i2c']
-    outputs = ['tca6408a']
+    outputs = []
+    tags = ['Embedded/industrial', 'IC']
     annotations = (
         ('register', 'Register type'),
         ('value', 'Register value'),
-        ('warnings', 'Warning messages'),
+        ('warning', 'Warning'),
     )
+    logic_output_channels = logic_channels(NUM_OUTPUT_CHANNELS)
     annotation_rows = (
         ('regs', 'Registers', (0, 1)),
         ('warnings', 'Warnings', (2,)),
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.state = 'IDLE'
         self.chip = -1
+        self.ss_logic = -1
 
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
+        self.out_logic = self.register(srd.OUTPUT_LOGIC)
 
     def putx(self, data):
         self.put(self.ss, self.es, self.out_ann, data)
 
+    def putl(self, data):
+        self.put(self.ss_logic, self.ss_logic, self.out_logic, data)
+
     def handle_reg_0x00(self, b):
         self.putx([1, ['State of inputs: %02X' % b]])
+        # TODO
 
     def handle_reg_0x01(self, b):
-        self.putx([1, ['Outputs set: %02X' % b ]])
+        self.putx([1, ['Outputs set: %02X' % b]])
+        self.ss_logic = self.ss
+        for i in range(NUM_OUTPUT_CHANNELS):
+            bit = (b & (1 << i)) != 0
+            self.putl([i, bytes([bit])])
 
     def handle_reg_0x02(self, b):
         self.putx([1, ['Polarity inverted: %02X' % b]])