##
import sigrokdecode as srd
-import re, traceback
+import re
'''
OUTPUT_PYTHON format:
('parity', 'PARITY'),
)
- def __init__(self, **kwargs):
+ def __init__(self):
# SWD data/clock state
self.state = 'UNKNOWN'
self.oldclk = -1
self.putp(ptype, (self.addr, self.data, self.ack))
def decode(self, ss, es, data):
- try:
- return self._decode(ss, es, data)
- except:
- traceback.print_exc()
- raise
-
- def _decode(self, ss, es, data):
for (self.samplenum, (clk, dio)) in data:
if clk == self.oldclk:
continue # Not a clock edge.
}[self.addr]
elif self.apdp == 'AP':
if self.rw == 'R':
- return 'W AP%x' % self.addr
+ return 'R AP%x' % self.addr
elif self.rw == 'W':
return 'W AP%x' % self.addr