## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-class Sample():
- def __init__(self, data):
- self.data = data
- def probe(self, probe):
- s = ord(self.data[probe / 8]) & (1 << (probe % 8))
- return True if s else False
-def sampleiter(data, unitsize):
- for i in range(0, len(data), unitsize):
- yield(Sample(data[i:i+unitsize]))
+import sigrokdecode as srd
-class Decoder():
- name = 'SPI Decoder'
+class Decoder(srd.Decoder):
+ id = 'spi'
+ name = 'SPI'
+ longname = 'Serial Peripheral Interface (SPI) bus'
desc = '...desc...'
- longname = '...longname...'
longdesc = '...longdesc...'
author = 'Gareth McMullin'
email = 'gareth@blacksphere.co.nz'
license = 'gplv2+'
inputs = ['logic']
outputs = ['spi']
- # Probe names with a set of defaults
- probes = {'sdata':0, 'sck':1}
+ probes = [
+ {'id': 'sdata', 'name': 'DATA', 'desc': 'SPI data line (MISO or MOSI)'},
+ {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
+ ]
options = {}
+ annotations = [
+ ['TODO', 'TODO'],
+ ]
- def __init__(self, unitsize, **kwargs):
- # Metadata comes in here, we don't care for now
- #print kwargs
- self.unitsize = unitsize
-
- self.probes = Decoder.probes.copy()
- self.oldsck = True
- self.rxcount = 0
+ def __init__(self):
+ self.oldsck = 1
+ self.bitcount = 0
self.rxdata = 0
self.bytesreceived = 0
+ def start(self, metadata):
+ # self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
+ self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
+
def report(self):
- return "SPI: %d bytes received" % self.bytesreceived
+ return 'SPI: %d bytes received' % self.bytesreceived
- def decode(self, data):
- # We should accept a list of samples and iterate...
- for sample in sampleiter(data["data"], self.unitsize):
+ def decode(self, ss, es, data):
+ # HACK! At the moment the number of probes is not handled correctly.
+ # E.g. if an input file (-i foo.sr) has more than two probes enabled.
+ # for (samplenum, (sdata, sck, x, y, z, a)) in data:
+ # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
+ for (samplenum, (cs, miso, sck, sdata, wp, hold)) in data:
- sck = sample.probe(self.probes["sck"])
- # Sample SDATA on rising SCK
+ # Sample SDATA on rising SCK.
if sck == self.oldsck:
continue
self.oldsck = sck
- if not sck:
- continue
-
- # If this is first bit, save timestamp
- if self.rxcount == 0:
- self.time = data["time"]
- # Receive bit into our shift register
- sdata = sample.probe(self.probes["sdata"])
- if sdata:
- self.rxdata |= 1 << (7 - self.rxcount)
- self.rxcount += 1
- # Continue to receive if not a byte yet
- if self.rxcount != 8:
+ if sck == 0:
continue
- # Received a byte, pass up to sigrok
- outdata = {"time":self.time,
- "duration":data["time"] + data["duration"] - self.time,
- "data":self.rxdata,
- "display":("%02X" % self.rxdata),
- "type":"spi",
- }
- sigrok.put(outdata)
- # Reset decoder state
- self.rxdata = 0
- self.rxcount = 0
- # Keep stats for summary
- self.bytesreceived += 1
-
-if __name__ == "__main__":
- data = open("spi_dump.bin").read()
- # dummy class to keep Decoder happy for test
- class Sigrok():
- def put(self, data):
- print "\t", data
- sigrok = Sigrok()
+ # If this is the first bit, save timestamp.
+ if self.bitcount == 0:
+ self.time = samplenum
- dec = Decoder(driver='ols', unitsize=1, starttime=0)
- dec.decode({"time":0, "duration":len(data), "data":data, "type":"logic"})
+ # Receive bit into our shift register.
+ if sdata == 1:
+ self.rxdata |= 1 << (7 - self.bitcount)
- print dec.summary()
-else:
- import sigrok
+ self.bitcount += 1
-#Tested with:
-# sigrok-cli -d 0:samplerate=1000000:rle=on --time=1s -p 1,2 -a spidec
+ # Continue to receive if not a byte yet.
+ if self.bitcount != 8:
+ continue
+
+ # self.put(0, 0, self.out_proto, out_proto) # TODO
+ self.put(0, 0, self.out_ann, [0, ['0x%02x' % self.rxdata]])
+ # Reset decoder state.
+ self.rxdata = 0
+ self.bitcount = 0
+
+ # Keep stats for summary.
+ self.bytesreceived += 1