['DATA', 0xff, 0x3a]
['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
[1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]],
- [[0, 80, 82], [0, 83, 84], [1, 85, 86], [1, 87, 88],
- [1, 89, 90], [0, 91, 92], [1, 93, 94], [0, 95, 96]]]
+ [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88],
+ [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]]
['DATA', 0x65, 0x00]
['DATA', 0xa8, None]
['DATA', None, 0x55]
license = 'gplv2+'
inputs = ['logic']
outputs = ['spi']
- probes = [
+ probes = (
{'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
- ]
- optional_probes = [
+ )
+ optional_probes = (
{'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
{'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
{'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
- ]
- options = {
- 'cs_polarity': ['CS# polarity', 'active-low'],
- 'cpol': ['Clock polarity', 0],
- 'cpha': ['Clock phase', 0],
- 'bitorder': ['Bit order within the SPI data', 'msb-first'],
- 'wordsize': ['Word size of SPI data', 8], # 1-64?
- 'format': ['Data format', 'hex'],
- }
- annotations = [
- ['miso-data', 'MISO data'],
- ['mosi-data', 'MOSI data'],
- ['miso-bits', 'MISO bits'],
- ['mosi-bits', 'MOSI bits'],
- ['warnings', 'Human-readable warnings'],
- ]
+ )
+ options = (
+ {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low',
+ 'values': ('active-low', 'active-high')},
+ {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0,
+ 'values': (0, 1)},
+ {'id': 'cpha', 'desc': 'Clock phase', 'default': 0,
+ 'values': (0, 1)},
+ {'id': 'bitorder', 'desc': 'Bit order within the SPI data',
+ 'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
+ {'id': 'wordsize', 'desc': 'Word size of SPI data', 'default': 8},
+ )
+ annotations = (
+ ('miso-data', 'MISO data'),
+ ('mosi-data', 'MOSI data'),
+ ('miso-bits', 'MISO bits'),
+ ('mosi-bits', 'MOSI bits'),
+ ('warnings', 'Human-readable warnings'),
+ )
annotation_rows = (
('miso-data', 'MISO data', (0,)),
('miso-bits', 'MISO bits', (2,)),
self.out_bitrate = self.register(srd.OUTPUT_META,
meta=(int, 'Bitrate', 'Bitrate during transfers'))
- def putpw(self, data):
- self.put(self.startsample, self.samplenum, self.out_python, data)
-
def putw(self, data):
self.put(self.startsample, self.samplenum, self.out_ann, data)
si = self.mosidata if self.have_mosi else None
so_bits = self.misobits if self.have_miso else None
si_bits = self.mosibits if self.have_mosi else None
- self.putpw(['BITS', si_bits, so_bits])
- self.putpw(['DATA', si, so])
+
+ if self.have_miso:
+ ss, es = self.misobits[-1][1], self.misobits[0][2]
+ if self.have_mosi:
+ ss, es = self.mosibits[-1][1], self.mosibits[0][2]
+
+ self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
+ self.put(ss, es, self.out_python, ['DATA', si, so])
# Bit annotations.
if self.have_miso:
# Dataword annotations.
if self.have_miso:
- ss, es = self.misobits[0][1], self.misobits[-1][2]
self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]])
if self.have_mosi:
- ss, es = self.mosibits[0][1], self.mosibits[-1][2]
self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]])
def reset_decoder_state(self):
# Guesstimate the endsample for this bit (can be overridden below).
es = self.samplenum
if self.bitcount > 0:
- es += self.samplenum - self.misobits[self.bitcount - 1][1]
+ if self.have_miso:
+ es += self.samplenum - self.misobits[0][1]
+ elif self.have_mosi:
+ es += self.samplenum - self.mosibits[0][1]
if self.have_miso:
- self.misobits.append([miso, self.samplenum, es])
+ self.misobits.insert(0, [miso, self.samplenum, es])
if self.have_mosi:
- self.mosibits.append([mosi, self.samplenum, es])
+ self.mosibits.insert(0, [mosi, self.samplenum, es])
if self.bitcount > 0 and self.have_miso:
- self.misobits[self.bitcount - 1][2] = self.samplenum
+ self.misobits[1][2] = self.samplenum
if self.bitcount > 0 and self.have_mosi:
- self.mosibits[self.bitcount - 1][2] = self.samplenum
+ self.mosibits[1][2] = self.samplenum
self.bitcount += 1