spi: Refactor for more coverage, and remove dead code.

[libsigrokdecode.git] / decoders / spi / pd.py

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index b1a87043c074005cb4d8cedf50dea7be0d870813..1ddb119c2729f1c2ff15972db887fc4482e8f15d 100644 (file)
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -24,10 +24,10 @@ import sigrokdecode as srd
 '''
 OUTPUT_PYTHON format:
 
-SPI packet:
-[<cmd>, <data1>, <data2>]
+Packet:
+[<ptype>, <data1>, <data2>]
 
-Commands:
+<ptype>:
  - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
    The data is _usually_ 8 bits (but can also be fewer or more bits).
    Both data items are Python numbers (not strings), or None if the respective
@@ -61,7 +61,7 @@ spi_mode = {
 }
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'spi'
     name = 'SPI'
     longname = 'Serial Peripheral Interface'
@@ -116,7 +116,6 @@ class Decoder(srd.Decoder):
         self.oldcs = -1
         self.oldpins = None
         self.have_cs = self.have_miso = self.have_mosi = None
-        self.state = 'IDLE'
 
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
@@ -174,9 +173,7 @@ class Decoder(srd.Decoder):
             self.cs_was_deasserted = False
             if self.have_cs:
                 active_low = (self.options['cs_polarity'] == 'active-low')
-                deasserted = (cs == 1) if active_low else (cs == 0)
-                if deasserted:
-                    self.cs_was_deasserted = True
+                self.cs_was_deasserted = (cs == 1) if active_low else (cs == 0)
 
         ws = self.options['wordsize']
 
@@ -278,9 +275,5 @@ class Decoder(srd.Decoder):
             if not (self.have_miso or self.have_mosi):
                 raise Exception('Either MISO or MOSI (or both) pins required.')
 
-            # State machine.
-            if self.state == 'IDLE':
-                self.find_clk_edge(miso, mosi, clk, cs)
-            else:
-                raise Exception('Invalid state: %s' % self.state)
+            self.find_clk_edge(miso, mosi, clk, cs)